Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: GlasgowEmbedded/glasgow
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: e53e8e2fce7e
Choose a base ref
...
head repository: GlasgowEmbedded/glasgow
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 43e6ffa7e8e0
Choose a head ref
  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Mar 19, 2019

  1. target.hardware: fix system clock constraint. 

    Something changed in Yosys and/or nextpnr and now they look for
the constraint on por_clk, not sys_clk, and silently ignore the one
on sys_clk. We need to fix that as well sometime...
    @whitequark
    whitequark committed Mar 19, 2019
    Copy the full SHA
    43e6ffa View commit details
Showing with 1 addition and 1 deletion.
  1. +1 −1 software/glasgow/target/hardware.py
2 changes: 1 addition & 1 deletion software/glasgow/target/hardware.py
View file
Original file line number Diff line number Diff line change
@@ -64,7 +64,7 @@ def __init__(self, revision, multiplexer_cls=None, with_analyzer=False):
pass

self.submodules.crg = _CRG(self.platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / self.sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_por.clk, 1e9 / self.sys_clk_freq)

self.submodules.i2c_pads = Pads(self.platform.request("i2c"))
self.submodules.i2c_slave = I2CSlave(self.i2c_pads)