GlasgowEmbedded · Mar 18, 2019 · Mar 18, 2019 · Mar 18, 2019
Showing with 23 additions and 13 deletions.

+1 −1 firmware/fifo.c

+5 −4 software/glasgow/applet/interface/spi_master/__init__.py

+3 −2 software/glasgow/applet/memory/_25x/__init__.py

+14 −6 software/glasgow/gateware/fx2.py
diff --git a/firmware/fifo.c b/firmware/fifo.c
@@ -41,7 +41,7 @@ void fifo_init() {
 }
 
 #define OUT_THRESHOLD 1U
-#define IN_THRESHOLD  510U
+#define IN_THRESHOLD  509U
 
 void fifo_configure(bool two_ep) {
   uint8_t ep26buf, ep48valid, ep26pkts;

diff --git a/software/glasgow/applet/interface/spi_master/__init__.py b/software/glasgow/applet/interface/spi_master/__init__.py
@@ -5,6 +5,7 @@
 from migen import *
 from migen.genlib.cdc import *
 
+from ....support.logging import *
 from ....gateware.clockgen import *
 from ... import *
 
@@ -216,14 +217,14 @@ async def transfer(self, data, hold_ss=False):
         assert len(data) <= 0xffff
         data = bytes(data)
 
-        self._log("xfer-out=<%s>", data.hex())
+        self._log("xfer-out=<%s>", dump_hex(data))
 
         cmd = CMD_XFER | (BIT_HOLD_SS if hold_ss else 0)
         await self.lower.write(struct.pack(">BH", cmd, len(data)))
         await self.lower.write(data)
         data = await self.lower.read(len(data))
 
-        self._log("xfer-in=<%s>", data.hex())
+        self._log("xfer-in=<%s>", dump_hex(data))
 
         return data
 
@@ -234,15 +235,15 @@ async def read(self, count, hold_ss=False):
         await self.lower.write(struct.pack(">BH", cmd, count))
         data = await self.lower.read(count)
 
-        self._log("read-in=<%s>", data.hex())
+        self._log("read-in=<%s>", dump_hex(data))
 
         return data
 
     async def write(self, data, hold_ss=False):
         assert len(data) <= 0xffff
         data = bytes(data)
 
-        self._log("write-out=<%s>", data.hex())
+        self._log("write-out=<%s>", dump_hex(data))
 
         cmd = CMD_WRITE | (BIT_HOLD_SS if hold_ss else 0)
         await self.lower.write(struct.pack(">BH", cmd, len(data)))

diff --git a/software/glasgow/applet/memory/_25x/__init__.py b/software/glasgow/applet/memory/_25x/__init__.py
@@ -7,6 +7,7 @@
 import logging
 import argparse
 
+from ....support.logging import dump_hex
 from ....database.jedec import *
 from ....protocol.sfdp import *
 from ...interface.spi_master import SPIMasterApplet
@@ -36,13 +37,13 @@ def _log(self, message, *args):
     async def _command(self, cmd, arg=[], dummy=0, ret=0, hold_ss=False):
         arg = bytes(arg)
 
-        self._log("cmd=%02X arg=<%s> dummy=%d ret=%d", cmd, arg.hex(), dummy, ret)
+        self._log("cmd=%02X arg=<%s> dummy=%d ret=%d", cmd, dump_hex(arg), dummy, ret)
 
         await self.lower.write(bytearray([cmd, *arg, *[0 for _ in range(dummy)]]),
                                hold_ss=(ret > 0))
         result = await self.lower.read(ret)
 
-        self._log("result=<%s>", result.hex())
+        self._log("result=<%s>", dump_hex(result))
 
         return result
 

diff --git a/software/glasgow/gateware/fx2.py b/software/glasgow/gateware/fx2.py
@@ -105,7 +105,6 @@ def __init__(self, fifo, asynchronous=False, auto_flush=True):
 
 class _RegisteredTristate(Module):
     def __init__(self, io):
-
         self.oe = Signal()
         self.o  = Signal.like(io)
         self.i  = Signal.like(io)
@@ -114,6 +113,18 @@ def get_bit(signal, bit):
             return signal[bit] if signal.nbits > 0 else signal
 
         for bit in range(io.nbits):
+            # The FX2 output valid window starts well after (5.4 ns past) the iCE40 input
+            # capture window for the rising edge. However, the input capture for
+            # the falling edge is just right.
+            #
+            # We carefully use DDR input and fabric registers to capture the FX2 output in
+            # the valid window and prolong its validity to 1 IFCLK cycle. The output is
+            # not DDR and is handled the straightforward way.
+            #
+            # See https://github.com/GlasgowEmbedded/Glasgow/issues/89 for details.
+
+            bit_r = Signal()
+            self.sync += get_bit(self.i, bit).eq(bit_r)
             self.specials += \
                 Instance("SB_IO",
                     # PIN_INPUT_REGISTERED|PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
@@ -123,11 +134,7 @@ def get_bit(signal, bit):
                     i_INPUT_CLK=ClockSignal(),
                     i_OUTPUT_CLK=ClockSignal(),
                     i_D_OUT_0=get_bit(self.o, bit),
-                    # The FX2 output valid window starts well after (5.4 ns past) the iCE40 input
-                    # capture window for the rising edge. However, the input capture for
-                    # the falling edge is just right.
-                    # See https://github.com/GlasgowEmbedded/Glasgow/issues/89 for details.
-                    o_D_IN_1=get_bit(self.i, bit),
+                    o_D_IN_1=bit_r,
                 )
 
 
@@ -229,6 +236,7 @@ def do_finalize(self):
             If(addr[1],
                 NextState("SETUP-IN")
             ).Else(
+                slrd.eq(1),
                 NextState("SETUP-OUT")
             )
         )