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whitequarkwhitequark
committedJul 27, 2018
applet.smia: new (partially functional) applet.
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‎software/glasgow/applet/__init__.py

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Original file line numberDiff line numberDiff line change
@@ -42,4 +42,5 @@ def run(self, device, args):
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from .i2c.eeprom import I2CEEPROMApplet
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from .program_ice40 import ProgramICE40Applet
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from .selftest import SelfTestApplet
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from .smia import SMIAApplet
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from .uart import UARTApplet

‎software/glasgow/applet/smia.py

Whitespace-only changes.

‎software/glasgow/applet/smia/__init__.py

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import logging
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import time
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from migen import *
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from .. import *
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from ..i2c_master import I2CMasterApplet
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from .smia_cci import SMIACCIInterface, SMIACamera
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logger = logging.getLogger(__name__)
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class SMIASubtarget(Module):
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def __init__(self, pads, reset):
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self.comb += [
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pads.xshutdown_t.oe.eq(1),
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pads.extclk_t.oe.eq(1),
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]
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reset_cyc = 1 << 16
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extclk_cyc = 2
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reset_timer = Signal(max=reset_cyc, reset=reset_cyc - 1)
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self.sync += [
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If(reset,
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reset_timer.eq(reset_timer.reset)
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).Elif(reset_timer != 0,
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reset_timer.eq(reset_timer - 1)
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)
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]
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self.comb += pads.xshutdown_t.o.eq(reset_timer == 0)
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extclk_timer = Signal(max=extclk_cyc, reset=extclk_cyc - 1)
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self.sync += [
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If(extclk_timer == 0,
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pads.extclk_t.o.eq(~pads.extclk_t.o),
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extclk_timer.eq(extclk_timer.reset)
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).Else(
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extclk_timer.eq(extclk_timer - 1)
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)
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]
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class CCP2Subtarget(Module):
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def __init__(self, pin_clk, pin_data, arbiter, errors):
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clk = Signal()
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data0 = Signal()
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data1 = Signal()
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self.specials += [
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Instance("SB_IO",
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p_PIN_TYPE=C(0b000001, 6), # PIN_INPUT
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io_PACKAGE_PIN=pin_clk,
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o_D_IN_0=clk,
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),
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Instance("SB_IO",
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p_PIN_TYPE=C(0b000000, 6), # PIN_INPUT_DDR
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io_PACKAGE_PIN=pin_data,
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i_INPUT_CLK=clk,
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o_D_IN_0=data0,
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o_D_IN_1=data1,
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),
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]
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self.clock_domains.cd_pix = ClockDomain()
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self.comb += self.cd_pix.clk.eq(clk)
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shreg = Signal(33)
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bitno = Signal(3)
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self.sync.pix += [
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shreg.eq(Cat(shreg[2:], data0, data1)),
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If(shreg[2:26] == C(0x0000ff, 24),
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bitno.eq(0)
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).Elif(shreg[3:27] == C(0x0000ff, 24),
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bitno.eq(1)
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).Else(
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bitno.eq(bitno + 2)
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)
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]
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in_fifo = arbiter.get_in_fifo(1, clock_domain=self.cd_pix)
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self.sync.pix += [
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If(bitno[0],
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in_fifo.din.eq(shreg[1:9])
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).Else(
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in_fifo.din.eq(shreg[0:8])
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),
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in_fifo.we.eq((bitno & ~1) == 0),
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]
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class SMIAApplet(I2CMasterApplet, name="smia"):
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logger = logger
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help = "capture image data from SMIA cameras"
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description = """
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Configure SMIA cameras via the CCI interface and capture image data via the CCP2 interface.
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"""
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@classmethod
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def add_build_arguments(cls, parser, access):
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super().add_build_arguments(parser, access)
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access.add_pin_argument(parser, "xshutdown", required=True)
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access.add_pin_argument(parser, "extclk", required=True)
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access.add_pin_argument(parser, "clk", required=True)
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access.add_pin_argument(parser, "data", required=True)
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def build(self, target, args):
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super().build(target, args)
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iface = self.mux_interface
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reset, self.__addr_reset = target.registers.add_rw(1, reset=1)
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target.submodules += SMIASubtarget(
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pads=iface.get_pads(args, pins=("xshutdown", "extclk")),
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reset=reset,
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)
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errors, self.__addr_errors = target.registers.add_ro()
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target.submodules += CCP2Subtarget(
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pin_clk=iface._pins[args.pin_clk],
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pin_data=iface._pins[args.pin_data],
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arbiter=iface._fx2_arbiter,
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errors=errors,
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)
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@classmethod
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def add_run_arguments(cls, parser, access):
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super().add_run_arguments(parser, access)
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parser.add_argument("-i", "--show-info", action="store_true", default=False,
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help="print camera information (model, manufacturer, etc)")
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parser.add_argument("-l", "--show-limits", action="store_true", default=False,
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help="print camera limits and capabilities (frequencies, gains, sizes, etc)")
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parser.add_argument("-c", "--show-clocking", action="store_true", default=False,
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help="print camera clocking configuration")
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def run(self, device, args):
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i2c_iface = super().run(device, args, interactive=False)
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cci_iface = SMIACCIInterface(i2c_iface, self.logger)
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camera = SMIACamera(cci_iface, self.logger, 15e6)
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device.set_voltage("A", 1.8)
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device.set_voltage("B", 2.7)
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device.write_register(self.__addr_reset, 1)
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i2c_iface.reset()
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time.sleep(0.050)
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device.write_register(self.__addr_reset, 0)
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time.sleep(0.050)
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if args.show_info:
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camera.show_info()
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if camera.get_smia_version() not in ((0, 9), (1, 0)):
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self.logger.error("unsupported SMIA version %d.%d", *camera.get_smia_version())
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if camera.get_smia_version() == (0, 0):
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self.logger.error("camera responded with SMIA version 0.0; is the power on?")
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self.logger.error("some cameras pull SDA/SCL lines to ground until both power "
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"supplies are on, in violation of the SMIA specification")
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return
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if args.show_limits:
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camera.show_limits()
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camera.set_ccp_data_format("RAW8")
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self.logger.info("autoconfiguring clocking")
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def clocking_constraints(config):
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return (config["op_sys_clk_freq_mhz"] <= 50.0 and
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config["vt_sys_clk_freq_mhz"] == config["op_sys_clk_freq_mhz"])
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if not camera.autoconfigure_clocking(clocking_constraints):
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self.logger.error("cannot automatically configure clocking")
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if args.show_clocking:
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camera.show_clocking_configuration()
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camera.set("test_pattern_mode", "ColourBars")
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camera.set("test_data_red", 0b10101010)
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camera.set("test_data_greenR", 0x00)
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camera.set("test_data_blue", 0x00)
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camera.set("test_data_greenB", 0x00)
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camera.start_streaming()
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print(device.bulk_read(8, 16384).hex())

‎software/glasgow/applet/smia/smia_cci.py

+783
Large diffs are not rendered by default.

‎software/glasgow/applet/smia/sub_lvds_buffer.py

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@@ -0,0 +1,78 @@
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import os
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import tempfile
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from migen import *
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from migen.build.generic_platform import *
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from migen.build.platforms.ice40_hx8k_b_evn import Platform as HX8KEvaluationPlatform
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_ext = [
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("clk_in", 0, Pins("C2")), # DP02B
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("clk_out", 0, Pins("D1")),
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("data_in", 0, Pins("J1")), # DP14B
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("data_out", 0, Pins("K3")),
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]
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class SubLVDSBuffer(Module):
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def __init__(self):
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self.platform = HX8KEvaluationPlatform()
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self.platform.add_extension(_ext)
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self.clock_domains.cd_sys = ClockDomain()
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counter = Signal(22)
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self.sync += counter.eq(counter - 1)
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led = self.platform.request("user_led")
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self.comb += led.eq(counter[counter.nbits - 1])
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clk = Signal()
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data = Signal()
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clk_in = self.platform.request("clk_in")
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data_in = self.platform.request("data_in")
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clk_out = self.platform.request("clk_out")
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data_out = self.platform.request("data_out")
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self.comb += self.cd_sys.clk.eq(~clk)
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clk_2 = Signal()
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self.sync += [
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clk_2.eq(~clk_2)
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]
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self.specials += [
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Instance("SB_IO",
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p_PIN_TYPE=C(0b000001, 6), # PIN_INPUT
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p_IO_STANDARD="SB_LVDS_INPUT",
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io_PACKAGE_PIN=clk_in,
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o_D_IN_0=clk,
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),
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Instance("SB_IO",
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p_PIN_TYPE=C(0b011000, 6), # PIN_OUTPUT
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io_PACKAGE_PIN=clk_out,
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i_D_OUT_0=clk_2,
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),
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Instance("SB_IO",
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p_PIN_TYPE=C(0b000001, 6), # PIN_INPUT
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p_IO_STANDARD="SB_LVDS_INPUT",
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io_PACKAGE_PIN=data_in,
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o_D_IN_0=data,
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),
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Instance("SB_IO",
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p_PIN_TYPE=C(0b011000, 6), # PIN_OUTPUT
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io_PACKAGE_PIN=data_out,
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i_D_OUT_0=data,
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),
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]
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def build_and_load(self, **kwargs):
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build_dir = tempfile.mkdtemp(prefix="sublvds_")
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self.platform.build(self, build_dir=build_dir, **kwargs)
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programmer = self.platform.create_programmer()
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programmer.load_bitstream(os.path.join(build_dir, "top.bin"))
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if __name__ == "__main__":
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sub_lvds_buffer = SubLVDSBuffer()
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sub_lvds_buffer.build_and_load()

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