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base repository: m-labs/nmigen
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compare: 9f643ce0059d
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  • 1 commit
  • 9 files changed
  • 1 contributor

Commits on Jun 4, 2019

  1. Clean up imports.

    This commit:
      * moves lists of universally useful imports from `nmigen` to
        `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
      * replaces lots of imports from individual parts of `nmigen.hdl`
        with a star import from `nmigen.hdl`;
      * replaces imports in tests with what we expect downstream code
        to use;
      * adds some missing imports in `nmigen.formal`.
    whitequark committed Jun 4, 2019
    Copy the full SHA
    9f643ce View commit details
12 changes: 2 additions & 10 deletions nmigen/__init__.py
Original file line number Diff line number Diff line change
@@ -2,13 +2,5 @@
__version__ = get_versions()['version']
del get_versions

from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
from .hdl.dsl import Module
from .hdl.cd import ClockDomain
from .hdl.ir import Elaboratable, Fragment, Instance
from .hdl.mem import Memory
from .hdl.rec import Record
from .hdl.xfrm import ResetInserter, CEInserter

from .lib.cdc import MultiReg
# from .lib.io import
from .hdl import *
from .lib import *
1 change: 1 addition & 0 deletions nmigen/formal.py
Original file line number Diff line number Diff line change
@@ -1 +1,2 @@
from .hdl.ast import AnyConst, AnySeq, Assert, Assume
from .hdl.ast import Past, Stable, Rose, Fell
7 changes: 7 additions & 0 deletions nmigen/hdl/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,7 @@
from .ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal
from .dsl import Module
from .cd import ClockDomain
from .ir import Elaboratable, Fragment, Instance
from .mem import Memory
from .rec import Record
from .xfrm import DomainRenamer, ResetInserter, CEInserter
1 change: 1 addition & 0 deletions nmigen/lib/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
from .cdc import MultiReg
4 changes: 1 addition & 3 deletions nmigen/test/test_lib_cdc.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,5 @@
from .tools import *
from ..hdl.ast import *
from ..hdl.cd import *
from ..hdl.dsl import *
from ..hdl import *
from ..back.pysim import *
from ..lib.cdc import *

5 changes: 2 additions & 3 deletions nmigen/test/test_lib_coding.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
from .tools import *
from ..hdl.ast import *
from ..hdl.dsl import *
from ..hdl.ir import *
from ..hdl import *
from ..formal import *
from ..back.pysim import *
from ..lib.coding import *

8 changes: 2 additions & 6 deletions nmigen/test/test_lib_fifo.py
Original file line number Diff line number Diff line change
@@ -1,10 +1,6 @@
from .tools import *
from ..hdl.ast import *
from ..hdl.dsl import *
from ..hdl.mem import *
from ..hdl.ir import *
from ..hdl.xfrm import *
from ..hdl.cd import *
from ..hdl import *
from ..formal import *
from ..back.pysim import *
from ..lib.fifo import *

3 changes: 2 additions & 1 deletion nmigen/test/test_lib_io.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from .tools import *
from ..hdl.ast import *
from ..hdl import *
from ..hdl.rec import *
from ..back.pysim import *
from ..lib.io import *


4 changes: 1 addition & 3 deletions nmigen/vendor/fpga/lattice_ice40.py
Original file line number Diff line number Diff line change
@@ -3,9 +3,7 @@
import subprocess
import tempfile

from ...hdl.ast import *
from ...hdl.dsl import *
from ...hdl.ir import *
from ...hdl import *
from ...build import *