Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 3adce21ce3bb
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 79a371025542
Choose a head ref
  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jun 4, 2019

  1. Copy the full SHA
    0cbb743 View commit details
  2. compat.fhdl.specials: fix platform lowering.

    get_tristate only has O/OE; the triple is created by get_input_output.
    whitequark committed Jun 4, 2019
    Copy the full SHA
    79a3710 View commit details
Showing with 4 additions and 4 deletions.
  1. +2 −2 nmigen/compat/fhdl/module.py
  2. +2 −2 nmigen/compat/fhdl/specials.py
4 changes: 2 additions & 2 deletions nmigen/compat/fhdl/module.py
Original file line number Diff line number Diff line change
@@ -83,12 +83,12 @@ def __iadd__(self, other):


class _CompatModuleClockDomains(_CompatModuleProxy):
@deprecated("TODO")
@deprecated("instead of `self.clock_domains.<name> =`, use `m.domains.<name> =`")
def __setattr__(self, name, value):
self.__iadd__(value)
setattr(self._cm, name, value)

@deprecated("TODO")
@deprecated("instead of `self.clock_domains +=`, use `m.domains +=`")
def __iadd__(self, other):
self._cm._module.domains += _flat_list(other)
return self
4 changes: 2 additions & 2 deletions nmigen/compat/fhdl/specials.py
Original file line number Diff line number Diff line change
@@ -39,8 +39,8 @@ def __init__(self, target, o, oe, i=None):
self.triple.i = i

def elaborate(self, platform):
if hasattr(platform, "get_tristate"):
return platform.get_tristate(self.triple, self.target)
if hasattr(platform, "get_input_output"):
return platform.get_input_output(self.triple, self.target, extras={})

m = Module()
m.d.comb += self.triple.i.eq(self.target)