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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 85efd083ea64
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  • 2 commits
  • 5 files changed
  • 1 contributor

Commits on Jun 4, 2019

  1. Copy the full SHA
    51c03ca View commit details
  2. build.res: use ConstraintError iff a constraint invariant is violated.

    In particular don't use it for type errors.
    whitequark committed Jun 4, 2019
    Copy the full SHA
    85efd08 View commit details
Showing with 32 additions and 9 deletions.
  1. +1 −0 nmigen/build/__init__.py
  2. +5 −5 nmigen/build/res.py
  3. +8 −4 nmigen/hdl/xfrm.py
  4. +2 −0 nmigen/test/test_hdl_ast.py
  5. +16 −0 nmigen/test/test_hdl_xfrm.py
1 change: 1 addition & 0 deletions nmigen/build/__init__.py
Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@
from .dsl import Pins, DiffPairs, Subsignal, Resource, Connector
from .res import ConstraintError
from .plat import Platform, TemplatedPlatform
10 changes: 5 additions & 5 deletions nmigen/build/res.py
Original file line number Diff line number Diff line change
@@ -56,9 +56,9 @@ def add_connectors(self, connectors):
def add_clock(self, name, number, frequency):
resource = self.lookup(name, number)
if isinstance(resource.io[0], Subsignal):
raise ConstraintError("Cannot constrain frequency of resource {}#{} because it has "
"subsignals"
.format(resource.name, resource.number, frequency))
raise TypeError("Cannot constrain frequency of resource {}#{} because it has "
"subsignals"
.format(resource.name, resource.number, frequency))
if (resource.name, resource.number) in self.clocks:
other = self.clocks[resource.name, resource.number]
raise ConstraintError("Resource {}#{} is already constrained to a frequency of "
@@ -68,8 +68,8 @@ def add_clock(self, name, number, frequency):

def lookup(self, name, number=0):
if (name, number) not in self.resources:
raise NameError("Resource {}#{} does not exist"
.format(name, number))
raise ConstraintError("Resource {}#{} does not exist"
.format(name, number))
return self.resources[name, number]

def request(self, name, number=0, *, dir=None, xdr=None):
12 changes: 8 additions & 4 deletions nmigen/hdl/xfrm.py
Original file line number Diff line number Diff line change
@@ -485,7 +485,9 @@ def groups(self):
return groups

def on_Assign(self, stmt):
self.unify(*stmt._lhs_signals())
lhs_signals = stmt._lhs_signals()
if lhs_signals:
self.unify(*stmt._lhs_signals())

on_Assert = on_Assign

@@ -511,9 +513,11 @@ def __init__(self, signals):
def on_Assign(self, stmt):
# The invariant provided by LHSGroupAnalyzer is that all signals that ever appear together
# on LHS are a part of the same group, so it is sufficient to check any of them.
any_lhs_signal = next(iter(stmt.lhs._lhs_signals()))
if any_lhs_signal in self.signals:
return stmt
lhs_signals = stmt.lhs._lhs_signals()
if lhs_signals:
any_lhs_signal = next(iter(lhs_signals))
if any_lhs_signal in self.signals:
return stmt

def on_Assert(self, stmt):
any_lhs_signal = next(iter(stmt._lhs_signals()))
2 changes: 2 additions & 0 deletions nmigen/test/test_hdl_ast.py
Original file line number Diff line number Diff line change
@@ -314,6 +314,8 @@ def test_repr(self):

class CatTestCase(FHDLTestCase):
def test_shape(self):
c0 = Cat()
self.assertEqual(c0.shape(), (0, False))
c1 = Cat(Const(10))
self.assertEqual(c1.shape(), (4, False))
c2 = Cat(Const(10), Const(1))
16 changes: 16 additions & 0 deletions nmigen/test/test_hdl_xfrm.py
Original file line number Diff line number Diff line change
@@ -303,6 +303,15 @@ def test_switch(self):
SignalSet((b,)),
])

def test_lhs_empty(self):
stmts = [
Cat().eq(0)
]

groups = LHSGroupAnalyzer()(stmts)
self.assertEqual(list(groups.values()), [
])


class LHSGroupFilterTestCase(FHDLTestCase):
def test_filter(self):
@@ -329,6 +338,13 @@ def test_filter(self):
)
""")

def test_lhs_empty(self):
stmts = [
Cat().eq(0)
]

self.assertRepr(LHSGroupFilter(SignalSet())(stmts), "()")


class ResetInserterTestCase(FHDLTestCase):
def setUp(self):