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base repository: m-labs/nmigen
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base: 9f643ce0059d
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head repository: m-labs/nmigen
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compare: 1b54eb80da11
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  • 3 commits
  • 14 files changed
  • 1 contributor

Commits on Jun 4, 2019

  1. Copy the full SHA
    2763b40 View commit details
  2. Copy the full SHA
    316ba10 View commit details
  3. vendor.board: split off into nmigen-boards package.

    The iCE40 programmers are also moved, since they're board-specific.
    (It looks like iceprog isn't, but it only works with Lattice
    evaluation kits.)
    
    Fixes #80.
    whitequark committed Jun 4, 2019
    Copy the full SHA
    1b54eb8 View commit details
2 changes: 1 addition & 1 deletion LICENSE.txt
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
Copyright (C) 2011-2018 M-Labs Limited
Copyright (C) 2011-2019 M-Labs Limited

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1 change: 1 addition & 0 deletions README.md
Original file line number Diff line number Diff line change
@@ -25,6 +25,7 @@ Thanks [LambdaConcept][] for being a sponsor of this project! Contact sb [at] m-
### Installation

pip install git+https://github.com/m-labs/nmigen.git
pip install git+https://github.com/m-labs/nmigen-boards.git

### Introduction

2 changes: 1 addition & 1 deletion examples/board/blinky.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
from nmigen import *
from nmigen.vendor.board.ice40_hx1k_blink_evn import *
from nmigen_boards.ice40_hx1k_blink_evn import *


class Blinky(Elaboratable):
8 changes: 8 additions & 0 deletions nmigen/build/res.py
Original file line number Diff line number Diff line change
@@ -183,6 +183,14 @@ def iter_port_constraints(self):
else:
assert False

def iter_port_constraints_bits(self):
for port_name, pin_names, extras in self.iter_port_constraints():
if len(pin_names) == 1:
yield port_name, pin_names[0], extras
else:
for bit, pin_name in enumerate(pin_names):
yield "{}[{}]".format(port_name, bit), pin_name, extras

def iter_clock_constraints(self):
for name, number in self.clocks.keys() & self._requested.keys():
resource = self.resources[name, number]
21 changes: 21 additions & 0 deletions nmigen/build/run.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,9 @@
from collections import OrderedDict
from contextlib import contextmanager
import os
import sys
import subprocess
import tempfile
import zipfile


@@ -60,3 +62,22 @@ def get(self, filename, mode="b"):
assert mode in "bt"
with open(os.path.join(self._root, filename), "r" + mode) as f:
return f.read()

@contextmanager
def extract(self, *filenames):
files = []
try:
for filename in filenames:
file = tempfile.NamedTemporaryFile(prefix="nmigen_", suffix="_" + filename)
files.append(file)
file.write(self.get(filename))

if len(files) == 0:
return (yield)
elif len(files) == 1:
return (yield files[0].name)
else:
return (yield [file.name for file in files])
finally:
for file in files:
file.close()
Empty file removed nmigen/vendor/board/__init__.py
Empty file.
34 changes: 0 additions & 34 deletions nmigen/vendor/board/ice40_hx1k_blink_evn.py

This file was deleted.

56 changes: 0 additions & 56 deletions nmigen/vendor/board/icestick.py

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55 changes: 0 additions & 55 deletions nmigen/vendor/board/tinyfpga_bx.py

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Empty file removed nmigen/vendor/conn/__init__.py
Empty file.
94 changes: 0 additions & 94 deletions nmigen/vendor/conn/pmod.py

This file was deleted.

Empty file removed nmigen/vendor/fpga/__init__.py
Empty file.
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