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nmigen_boards/_version.py export-subst |
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*.pyc | ||
*.egg-info | ||
/build |
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Copyright (C) 2011-2019 M-Labs Limited | ||
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Redistribution and use in source and binary forms, with or without modification, | ||
are permitted provided that the following conditions are met: | ||
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1. Redistributions of source code must retain the above copyright notice, this | ||
list of conditions and the following disclaimer. | ||
2. Redistributions in binary form must reproduce the above copyright notice, | ||
this list of conditions and the following disclaimer in the documentation | ||
and/or other materials provided with the distribution. | ||
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND | ||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | ||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR | ||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | ||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | ||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | ||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
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Other authors retain ownership of their contributions. If a submission can | ||
reasonably be considered independently copyrightable, it's yours and we | ||
encourage you to claim it with appropriate copyright notices. This submission | ||
then falls under the "otherwise noted" category. All submissions are strongly | ||
encouraged to use the two-clause BSD license reproduced above. |
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# nMigen boards and connectors | ||
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## Ready to use board and extension connector pinouts, and programming scripts | ||
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TBD | ||
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### License | ||
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nMigen is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use nMigen for closed-source proprietary designs. | ||
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See LICENSE file for full copyright and license info. |
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# Reference: https://www.digilentinc.com/Pmods/Digilent-Pmod_%20Interface_Specification.pdf | ||
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from nmigen.build import * | ||
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__all__ = [ | ||
"PmodGPIOType1Resource", | ||
"PmodSPIType2Resource", | ||
"PmodSPIType2AResource", | ||
"PmodUARTType3Resource", | ||
"PmodUARTType4Resource", | ||
"PmodUARTType4AResource", | ||
"PmodHBridgeType5Resource", | ||
"PmodDualHBridgeType6Resource", | ||
] | ||
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def PmodGPIOType1Resource(name, number, *, pmod, extras=None): | ||
return Resource(name, number, | ||
Pins("1 2 3 4", dir="io", conn=("pmod", pmod)), | ||
extras=extras | ||
) | ||
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def PmodSPIType2Resource(name, number, *, pmod, extras=None): | ||
return Resource(name, number, | ||
Subsignal("cs_n", Pins("1", dir="o", conn=("pmod", pmod))), | ||
Subsignal("clk", Pins("2", dir="o", conn=("pmod", pmod))), | ||
Subsignal("mosi", Pins("3", dir="o", conn=("pmod", pmod))), | ||
Subsignal("miso", Pins("4", dir="i", conn=("pmod", pmod))), | ||
extras=extras | ||
) | ||
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def PmodSPIType2AResource(name, number, *, pmod, extras=None): | ||
return Resource(name, number, | ||
Subsignal("cs_n", Pins("1", dir="o", conn=("pmod", pmod))), | ||
Subsignal("clk", Pins("2", dir="o", conn=("pmod", pmod))), | ||
Subsignal("mosi", Pins("3", dir="o", conn=("pmod", pmod))), | ||
Subsignal("miso", Pins("4", dir="i", conn=("pmod", pmod))), | ||
Subsignal("int", Pins("7", dir="i", conn=("pmod", pmod))), | ||
Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))), | ||
extras=extras | ||
) | ||
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def PmodUARTType3Resource(name, number, *, pmod, extras=None): | ||
return Resource(name, number, | ||
Subsignal("cts", Pins("1", dir="o", conn=("pmod", pmod))), | ||
Subsignal("rts", Pins("2", dir="i", conn=("pmod", pmod))), | ||
Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))), | ||
Subsignal("tx", Pins("4", dir="o", conn=("pmod", pmod))), | ||
extras=extras | ||
) | ||
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def PmodUARTType4Resource(name, number, *, pmod, extras=None): | ||
return Resource(name, number, | ||
Subsignal("cts", Pins("1", dir="i", conn=("pmod", pmod))), | ||
Subsignal("tx", Pins("2", dir="o", conn=("pmod", pmod))), | ||
Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))), | ||
Subsignal("rts", Pins("4", dir="o", conn=("pmod", pmod))), | ||
extras=extras | ||
) | ||
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def PmodUARTType4AResource(name, number, *, pmod, extras=None): | ||
return Resource(name, number, | ||
Subsignal("cts", Pins("1", dir="i", conn=("pmod", pmod))), | ||
Subsignal("tx", Pins("2", dir="o", conn=("pmod", pmod))), | ||
Subsignal("rx", Pins("3", dir="i", conn=("pmod", pmod))), | ||
Subsignal("rts", Pins("4", dir="o", conn=("pmod", pmod))), | ||
Subsignal("int", Pins("7", dir="i", conn=("pmod", pmod))), | ||
Subsignal("reset", Pins("8", dir="o", conn=("pmod", pmod))), | ||
extras=extras | ||
) | ||
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def PmodHBridgeType5Resource(name, number, *, pmod, extras=None): | ||
return Resource(name, number, | ||
Subsignal("dir", Pins("1", dir="o", conn=("pmod", pmod))), | ||
Subsignal("en", Pins("2", dir="o", conn=("pmod", pmod))), | ||
Subsignal("sa", Pins("3", dir="i", conn=("pmod", pmod))), | ||
Subsignal("sb", Pins("4", dir="i", conn=("pmod", pmod))), | ||
extras=extras | ||
) | ||
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def PmodDualHBridgeType6Resource(name, number, *, pmod, extras=None): | ||
return Resource(name, number, | ||
Subsignal("dir", Pins("1 3", dir="o", conn=("pmod", pmod))), | ||
Subsignal("en", Pins("2 4", dir="o", conn=("pmod", pmod))), | ||
extras=extras | ||
) |
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import os | ||
import subprocess | ||
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from nmigen.build import * | ||
from nmigen.vendor.lattice_ice40 import * | ||
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__all__ = ["ICE40HX1KBlinkEVNPlatform"] | ||
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class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform): | ||
device = "hx1k" | ||
package = "vq100" | ||
clocks = [ | ||
("clk3p3", 3.3e6), | ||
] | ||
resources = [ | ||
Resource("clk3p3", 0, Pins("13", dir="i"), | ||
extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}), | ||
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Resource("user_led", 0, Pins("59", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_led", 1, Pins("56", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_led", 2, Pins("53", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_led", 3, Pins("51", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
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Resource("user_btn", 0, Pins("60"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_btn", 1, Pins("57"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_btn", 2, Pins("54"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_btn", 3, Pins("52"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
] | ||
connectors = [ | ||
Connector("pmod", 1, "10 9 8 7 - - 4 3 2 1 - -"), # J1 | ||
Connector("pmod", 5, "40 42 62 64 - - 37 41 63 45 - -"), # J5 | ||
Connector("pmod", 6, "25 24 21 20 - - 26 27 28 33 - -"), # J6 | ||
Connector("pmod", 11, "49 45 46 48 - -"), # J11 | ||
Connector("pmod", 12, "59 56 53 51 - -"), # J12 | ||
] | ||
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def toolchain_program(self, products, name): | ||
iceburn = os.environ.get("ICEBURN", "iCEburn") | ||
with products.extract("{}.bin".format(name)) as bitstream_filename: | ||
subprocess.run([iceburn, "-evw", bitstream_filename], check=True) |
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import os | ||
import subprocess | ||
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from nmigen.build import * | ||
from nmigen.vendor.lattice_ice40 import * | ||
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__all__ = ["ICEStickPlatform"] | ||
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class ICEStickPlatform(LatticeICE40Platform): | ||
device = "hx1k" | ||
package = "tq144" | ||
clocks = [ | ||
("clk12", 12e6), | ||
] | ||
resources = [ | ||
Resource("clk12", 0, Pins("21", dir="i"), | ||
extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}), | ||
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Resource("user_led", 0, Pins("99", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_led", 1, Pins("98", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_led", 2, Pins("97", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_led", 3, Pins("96", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
Resource("user_led", 4, Pins("95", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
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Resource("serial", 0, | ||
Subsignal("rx", Pins("9", dir="i")), | ||
Subsignal("tx", Pins("8", dir="o")), | ||
Subsignal("rts", Pins("7", dir="o")), | ||
Subsignal("cts", Pins("4", dir="i")), | ||
Subsignal("dtr", Pins("3", dir="o")), | ||
Subsignal("dsr", Pins("2", dir="i")), | ||
Subsignal("dcd", Pins("1", dir="i")), | ||
extras={"IO_STANDARD": "SB_LVTTL", "PULLUP": "1"} | ||
), | ||
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Resource("irda", 0, | ||
Subsignal("rx", Pins("106", dir="i")), | ||
Subsignal("tx", Pins("105", dir="o")), | ||
Subsignal("sd", Pins("107", dir="o")), | ||
extras={"IO_STANDARD": "SB_LVCMOS33"} | ||
), | ||
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Resource("spiflash", 0, | ||
Subsignal("cs_n", Pins("71", dir="o")), | ||
Subsignal("clk", Pins("70", dir="o")), | ||
Subsignal("mosi", Pins("67", dir="o")), | ||
Subsignal("miso", Pins("68", dir="i")), | ||
extras={"IO_STANDARD": "SB_LVCMOS33"} | ||
), | ||
] | ||
connectors = [ | ||
Connector("pmod", 0, "78 79 80 81 - - 87 88 90 91 - -"), # J2 | ||
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Connector("j", 1, "- - 112 113 114 115 116 117 118 119"), # J1 | ||
Connector("j", 3, "- - 62 61 60 56 48 47 45 44"), # J3 | ||
] | ||
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def toolchain_program(self, products, name): | ||
iceprog = os.environ.get("ICEPROG", "iceprog") | ||
with products.extract("{}.bin".format(name)) as bitstream_filename: | ||
subprocess.run([iceprog, bitstream_filename], check=True) |
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import os | ||
import subprocess | ||
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from nmigen.build import * | ||
from nmigen.vendor.lattice_ice40 import * | ||
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__all__ = ["TinyFPGABXPlatform"] | ||
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class TinyFPGABXPlatform(LatticeICE40Platform): | ||
device = "lp8k" | ||
package = "cm81" | ||
clocks = [ | ||
("clk16", 16e6), | ||
] | ||
resources = [ | ||
Resource("clk16", 0, Pins("B2", dir="i"), | ||
extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
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Resource("user_led", 0, Pins("B3", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}), | ||
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Resource("usb", 0, | ||
Subsignal("d_p", Pins("B4", dir="io")), | ||
Subsignal("d_n", Pins("A4", dir="io")), | ||
Subsignal("pullup", Pins("A3", dir="o")), | ||
extras={"IO_STANDARD": "SB_LVCMOS33"} | ||
), | ||
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Resource("spiflash", 0, | ||
Subsignal("cs_n", Pins("F7", dir="o")), | ||
Subsignal("clk", Pins("G7", dir="o")), | ||
Subsignal("mosi", Pins("G6", dir="o")), | ||
Subsignal("miso", Pins("H7", dir="i")), | ||
Subsignal("wp", Pins("H4", dir="o")), | ||
Subsignal("hold", Pins("J8", dir="o")), | ||
extras={"IO_STANDARD": "SB_LVCMOS33"} | ||
), | ||
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Resource("spiflash4x", 0, | ||
Subsignal("cs_n", Pins("F7", dir="o")), | ||
Subsignal("clk", Pins("G7", dir="o")), | ||
Subsignal("dq", Pins("G6 H7 H4 J8", dir="io")), | ||
extras={"IO_STANDARD": "SB_LVCMOS33"} | ||
), | ||
] | ||
connectors = [ | ||
Connector("gpio", 0, | ||
# Left side of the board | ||
# 1 2 3 4 5 6 7 8 9 10 11 12 13 | ||
" A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2" | ||
# Right side of the board | ||
# 14 15 16 17 18 19 20 21 22 23 24 | ||
" H9 D9 D8 B8 A9 B8 A8 B7 A7 B6 A6" | ||
# Bottom of the board | ||
# 25 26 27 28 29 30 31 | ||
"G1 J3 J4 G9 J9 E8 J2"), | ||
] | ||
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def toolchain_program(self, products, name): | ||
tinyprog = os.environ.get("TINYPROG", "tinyprog") | ||
with products.extract("{}.bin".format(name)) as bitstream_filename: | ||
subprocess.run([tinyprog, "-p", bitstream_filename], check=True) |
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[versioneer] | ||
VCS = git | ||
style = git-describe-long | ||
versionfile_source = nmigen_boards/_version.py | ||
versionfile_build = nmigen_boards/_version.py | ||
tag_prefix = v | ||
parentdir_prefix = nmigen_boards- |
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import sys | ||
from setuptools import setup, find_packages | ||
import versioneer | ||
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setup( | ||
name="nmigen-boards", | ||
version=versioneer.get_version(), | ||
author="whitequark", | ||
author_email="whitequark@whitequark.org", | ||
description="Board and connector definitions for nMigen", | ||
#long_description="""TODO""", | ||
license="BSD", | ||
install_requires=["nmigen"], | ||
packages=find_packages(), | ||
project_urls={ | ||
"Source Code": "https://github.com/m-labs/nmigen-boards", | ||
"Bug Tracker": "https://github.com/m-labs/nmigen-boards/issues", | ||
}, | ||
cmdclass=versioneer.get_cmdclass() | ||
) |
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