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base repository: m-labs/nmigen
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base: c9879c795bf7
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head repository: m-labs/nmigen
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compare: b45c5119f573
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Jun 5, 2019

  1. Copy the full SHA
    b45c511 View commit details
Showing with 27 additions and 6 deletions.
  1. +15 −6 nmigen/build/res.py
  2. +12 −0 nmigen/test/test_build_res.py
21 changes: 15 additions & 6 deletions nmigen/build/res.py
Original file line number Diff line number Diff line change
@@ -191,11 +191,9 @@ def iter_port_constraints_bits(self):
for bit, pin_name in enumerate(pin_names):
yield "{}[{}]".format(port_name, bit), pin_name, attrs

def add_clock_constraint(self, clock, frequency):
def _map_clock_to_port(self, clock):
if not isinstance(clock, (Signal, Pin)):
raise TypeError("Object {!r} is not a Signal or Pin".format(clock))
if not isinstance(frequency, (int, float)):
raise TypeError("Frequency must be a number, not {!r}".format(frequency))

if isinstance(clock, Pin):
for res, pin, port, attrs in self._ports:
@@ -208,16 +206,27 @@ def add_clock_constraint(self, clock, frequency):
assert False
break
else:
raise ValueError("Cannot add clock constraint on a Pin {!r} that is not "
"a previously requested resource"
raise ValueError("The Pin object {!r}, which is not a previously requested "
"resource, cannot be used to desigate a clock"
.format(clock))

return clock

def add_clock_constraint(self, clock, frequency):
if not isinstance(frequency, (int, float)):
raise TypeError("Frequency must be a number, not {!r}".format(frequency))

clock = self._map_clock_to_port(clock)
if clock in self._clocks:
raise ValueError("Cannot add clock constraint on {!r}, which is already constrained "
"to {} Hz"
.format(clock, self._clocks[clock]))
else:
self._clocks[clock] = float(frequency)

self._clocks[clock] = float(frequency)
def get_clock_constraint(self, clock):
clock = self._map_clock_to_port(clock)
return self._clocks[clock]

def iter_clock_constraints(self):
return iter(self._clocks.items())
12 changes: 12 additions & 0 deletions nmigen/test/test_build_res.py
Original file line number Diff line number Diff line change
@@ -168,6 +168,12 @@ def test_add_clock(self):
(scl_port, 100e3)
])

def test_get_clock(self):
clk100 = self.cm.request("clk100", 0)
self.assertEqual(self.cm.get_clock_constraint(clk100), 100e6)
with self.assertRaises(KeyError):
self.cm.get_clock_constraint(Signal())

def test_wrong_resources(self):
with self.assertRaises(TypeError, msg="Object 'wrong' is not a Resource"):
self.cm.add_resources(['wrong'])
@@ -203,6 +209,12 @@ def test_wrong_clock_frequency(self):
msg="Frequency must be a number, not None"):
self.cm.add_clock_constraint(Signal(), None)

def test_wrong_clock_pin(self):
with self.assertRaises(ValueError,
msg="The Pin object (rec <unnamed> i), which is not a previously requested "
"resource, cannot be used to desigate a clock"):
self.cm.add_clock_constraint(Pin(1, dir="i"), 1e6)

def test_wrong_request_duplicate(self):
with self.assertRaises(ResourceError,
msg="Resource user_led#0 has already been requested"):