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Platform clock definitions are very inflexible #86
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I propose that instead of declaring a resource or subsignal a clock at the top level, it would be done as follows: class TinyFPGABXPlatform(LatticeICE40Platform):
device = "iCE40LP8K"
package = "CM81"
resources = [
Resource("clk16", 0, Pins("B2", dir="i"),
extras={"IO_STANDARD": "SB_LVCMOS33"},
frequency=16e6),
# ...
] Bikeshed: maybe this would be slightly more elegant? class TinyFPGABXPlatform(LatticeICE40Platform):
device = "iCE40LP8K"
package = "CM81"
resources = [
Resource("clk16", 0, Pins("B2", dir="i"), Clock(16e6),
Extras(IO_STANDARD="SB_LVCMOS33")),
# ...
] The implementation would be similar to the current one: the |
Just to add a data point: Some platforms, TinyFPGA A in particular, don't actually have a clock pin, instead relying on the FPGA's internal oscillator. I did some things I'm not exactly proud of to get it to play nice with So if there is a way to more nicely support internal clock constraints or otherwise without a |
Right, so that's a related but different situation: defining frequency constraints on ports and on nets. Currently nextpnr is deficient in that it does not allow to reliably define a frequency constraint on a net, so we're going to have to teach |
Right now, platform clocks are defined like this:
There is a problem though: it is only possible to declare a top-level resource as a clock (i.e. not a subsignal). Something like Versa has this resource in oMigen:
which has custom code to add clock constraints in
do_finalize
.The text was updated successfully, but these errors were encountered: