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base repository: m-labs/nmigen-boards
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head repository: m-labs/nmigen-boards
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compare: ec6316eb3341
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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Jun 4, 2019

  1. Copy the full SHA
    e8dcc1e View commit details

Commits on Jun 5, 2019

  1. Update to track changes in nmigen.

    whitequark committed Jun 5, 2019
    Copy the full SHA
    ec6316e View commit details
Showing with 53 additions and 51 deletions.
  1. +10 −7 nmigen_boards/_blinky.py
  2. +23 −18 nmigen_boards/ice40_hx1k_blink_evn.py
  3. +12 −15 nmigen_boards/icestick.py
  4. +8 −11 nmigen_boards/tinyfpga_bx.py
17 changes: 10 additions & 7 deletions nmigen_boards/_blinky.py
Original file line number Diff line number Diff line change
@@ -1,27 +1,30 @@
import itertools

from nmigen import *
from nmigen.build import ConstraintError
from nmigen.build import ResourceError


class Blinky(Elaboratable):
def __init__(self, clk_name, clk_freq):
self.clk_name = clk_name
self.clk_freq = clk_freq

def elaborate(self, platform):
m = Module()

clk_name, clk_freq = next(iter(platform.clocks.items()))
clk = platform.request(*clk_name)
clk = platform.request(self.clk_name)
m.domains.sync = ClockDomain()
m.d.comb += ClockSignal().eq(clk.i)

leds = []
for n in itertools.count():
try:
leds.append(platform.request("user_led", n))
except ConstraintError:
except ResourceError:
break
leds = Cat(led.o for led in leds)

ctr = Signal(max=int(clk_freq//2), reset=int(clk_freq//2) - 1)
ctr = Signal(max=int(self.clk_freq//2), reset=int(self.clk_freq//2) - 1)
with m.If(ctr == 0):
m.d.sync += ctr.eq(ctr.reset)
m.d.sync += leds.eq(~leds)
@@ -31,5 +34,5 @@ def elaborate(self, platform):
return m


def build_and_program(platform_cls, **kwargs):
platform_cls().build(Blinky(), do_program=True, **kwargs)
def build_and_program(platform_cls, clk_name, clk_freq, **kwargs):
platform_cls().build(Blinky(clk_name, clk_freq), do_program=True, **kwargs)
41 changes: 23 additions & 18 deletions nmigen_boards/ice40_hx1k_blink_evn.py
Original file line number Diff line number Diff line change
@@ -9,24 +9,29 @@


class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
device = "hx1k"
package = "vq100"
clocks = [
("clk3p3", 3.3e6),
]
device = "iCE40HX1K"
package = "VQ100"
resources = [
Resource("clk3p3", 0, Pins("13", dir="i"),
extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),

Resource("user_led", 0, Pins("59", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 1, Pins("56", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 2, Pins("53", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 3, Pins("51", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),

Resource("user_btn", 0, Pins("60"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_btn", 1, Pins("57"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_btn", 2, Pins("54"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_btn", 3, Pins("52"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("clk3p3", 0, Pins("13", dir="i"), Clock(3.3e6),
Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),

Resource("user_led", 0, Pins("59", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_led", 1, Pins("56", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_led", 2, Pins("53", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_led", 3, Pins("51", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),

Resource("user_btn", 0, Pins("60"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_btn", 1, Pins("57"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_btn", 2, Pins("54"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_btn", 3, Pins("52"), Attrs(IO_STANDARD="SB_LVCMOS33")),

Resource("spiflash", 0,
Subsignal("cs_n", Pins("49", dir="o")),
Subsignal("clk", Pins("48", dir="o")),
Subsignal("mosi", Pins("45", dir="o")),
Subsignal("miso", Pins("46", dir="i")),
Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
Connector("pmod", 1, "10 9 8 7 - - 4 3 2 1 - -"), # J1
@@ -44,4 +49,4 @@ def toolchain_program(self, products, name):

if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(ICE40HX1KBlinkEVNPlatform)
build_and_program(ICE40HX1KBlinkEVNPlatform, "clk3p3", 3.3e6)
27 changes: 12 additions & 15 deletions nmigen_boards/icestick.py
Original file line number Diff line number Diff line change
@@ -9,20 +9,17 @@


class ICEStickPlatform(LatticeICE40Platform):
device = "hx1k"
package = "tq144"
clocks = [
("clk12", 12e6),
]
device = "iCE40HX1K"
package = "TQ144"
resources = [
Resource("clk12", 0, Pins("21", dir="i"),
extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),
Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),

Resource("user_led", 0, Pins("99", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 1, Pins("98", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 2, Pins("97", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 3, Pins("96", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 4, Pins("95", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 0, Pins("99", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_led", 1, Pins("98", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_led", 2, Pins("97", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_led", 3, Pins("96", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),
Resource("user_led", 4, Pins("95", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),

Resource("serial", 0,
Subsignal("rx", Pins("9", dir="i")),
@@ -32,22 +29,22 @@ class ICEStickPlatform(LatticeICE40Platform):
Subsignal("dtr", Pins("3", dir="o")),
Subsignal("dsr", Pins("2", dir="i")),
Subsignal("dcd", Pins("1", dir="i")),
extras={"IO_STANDARD": "SB_LVTTL", "PULLUP": "1"}
Attrs(IO_STANDARD="SB_LVTTL", PULLUP="1")
),

Resource("irda", 0,
Subsignal("rx", Pins("106", dir="i")),
Subsignal("tx", Pins("105", dir="o")),
Subsignal("sd", Pins("107", dir="o")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
Attrs(IO_STANDARD="SB_LVCMOS33")
),

Resource("spiflash", 0,
Subsignal("cs_n", Pins("71", dir="o")),
Subsignal("clk", Pins("70", dir="o")),
Subsignal("mosi", Pins("67", dir="o")),
Subsignal("miso", Pins("68", dir="i")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
@@ -65,4 +62,4 @@ def toolchain_program(self, products, name):

if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(ICEStickPlatform)
build_and_program(ICEStickPlatform, "clk12", 12e6)
19 changes: 8 additions & 11 deletions nmigen_boards/tinyfpga_bx.py
Original file line number Diff line number Diff line change
@@ -9,22 +9,19 @@


class TinyFPGABXPlatform(LatticeICE40Platform):
device = "lp8k"
package = "cm81"
clocks = [
("clk16", 16e6),
]
device = "iCE40LP8K"
package = "CM81"
resources = [
Resource("clk16", 0, Pins("B2", dir="i"),
extras={"IO_STANDARD": "SB_LVCMOS33"}),
Clock(16e6), Attrs(IO_STANDARD="SB_LVCMOS33")),

Resource("user_led", 0, Pins("B3", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
Resource("user_led", 0, Pins("B3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")),

Resource("usb", 0,
Subsignal("d_p", Pins("B4", dir="io")),
Subsignal("d_n", Pins("A4", dir="io")),
Subsignal("pullup", Pins("A3", dir="o")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
Attrs(IO_STANDARD="SB_LVCMOS33")
),

Resource("spiflash", 0,
@@ -34,14 +31,14 @@ class TinyFPGABXPlatform(LatticeICE40Platform):
Subsignal("miso", Pins("H7", dir="i")),
Subsignal("wp", Pins("H4", dir="o")),
Subsignal("hold", Pins("J8", dir="o")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
Attrs(IO_STANDARD="SB_LVCMOS33")
),

Resource("spiflash4x", 0,
Subsignal("cs_n", Pins("F7", dir="o")),
Subsignal("clk", Pins("G7", dir="o")),
Subsignal("dq", Pins("G6 H7 H4 J8", dir="io")),
extras={"IO_STANDARD": "SB_LVCMOS33"}
Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
connectors = [
@@ -65,4 +62,4 @@ def toolchain_program(self, products, name):

if __name__ == "__main__":
from ._blinky import build_and_program
build_and_program(TinyFPGABXPlatform)
build_and_program(TinyFPGABXPlatform, "clk16", 16e6)