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Invalid Verilog generated for .bool() of zero-width slice #41
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That's a Yosys bug, since Yosys is what writes the Verilog in the first place. |
You're 100% right, sorry. This is the ilang nMigen generates:
And this is syntactically valid as it's deliberately special-cased in
However the sequence By the way this wasn't deliberate troublemaking, I had some code that looked like this:
and I guess there's a secondary question on this issue, namely, is this intended to be valid in nMigen? |
I think zero width values are perfectly reasonable. We currently don't support zero width signals, mostly for historic reasons; I'm less certain about those but it probably makes sense to support those too. |
Actually, we do support them, which is good. |
Ah, thank you for the poke, sorry. I think I got lost in the Verilog LRM
for a couple days while drafting the Yosys issue. Will get on this.
…On Wed, 10 Apr 2019, 01:28 whitequark, ***@***.***> wrote:
We currently don't support zero width *signals*, mostly for historic
reasons
Actually, we do support them, which is good.
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Clifford's reponse on Yosys issue:
The Yosys patch just generates an empty Verilog string literal when a zero-width expression is encountered. The resulting Verilog synthesises fine with Yosys, so I think this issue can be closed. However as Clifford said, this is a dingy corner of the standard, so perhaps:
I also note that that same warning ^^^ is produced for the full nMigen pipeline of
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Ugh, that's annoying. I think if Yosys doesn't want to support zero-width signals in RTLIL or write_verilog it should enforce that. Otherwise the current situation is fine. Thanks for investigating. |
Repro:
The generated file contains an empty concat list. On the other hand, this seems to work fine:
This is with nMigen master and a very recent Yosys.
Designs doing this kind of slice simulate fine, and
Signal(0).bool() == Signal(n)[:0].bool() == 0
which makes sense to me. (Is this written down anywhere? Verilog does an awful job of 0-width signals, but they're a useful generalisation, take a lot of edge cases out of your code)The text was updated successfully, but these errors were encountered: