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Assert passes when it should fail #193
Comments
Note, I'm generating |
Just a quick check, what happens if you use |
(That doesn't change anything.) |
I'm afraid I do not know, and can't find, how to use Symbiyosys with an rtlil file. |
Replace |
Still passes the assert, when it shouldn't. |
Yep, see above comment. Looking at it now. |
I think the problem is that:
is not the same as:
Specifically, the |
Ah, ok. Yeah, that makes sense. It isn't exactly the same, though, is it? Because then the nMigen source doesn't specify that Really what I want is something like
|
It does: nMigen doesn't have |
Oh and |
Hmm, what's the equivalent of the Yosys-specific
Is it just
|
Yes, |
Hmm, that seems to lead to an error from sby:
It seems to translate
to
|
Are you still going through SystemVerilog, or are you feeding RTLIL directly to SymbiYosys? |
Through SV. I did try it with RTLIL and it was ok, so now I have to add back my tests... |
OK, here are the next two pairs that seem equivalent but aren't. We have a We want The SV source correctly passes, while the nMigen source seems to fail with a warmup failure. Maybe it's because nMigen:
SV:
|
You can reproduce the I'm not sure exactly what you're trying to do, so I'm not sure which solution would be appropriate here. Obviously, assigning |
Ah, ok, so that's the contradiction in assumptions that's going on:
|
Yes. You might want to use |
Argh. According to this,
In fact, none of these lines force the failure:
|
Yes. You can't drive a domain reset signal from the very domain that it resets, at least not without making the |
Ah, yes, that makes sense. Making |
assert_fail.py
is nMigen source, andassert_pass.sv
should be the equivalent SV code. However, the Assert inassert_fail.py
passes when it should not.failme.sby
runs Symbiyosys againstassert_fail.py
and erroneously passes.passme.sby
runs Symbiyosys againstassert_pass.sv
and correctly fails.assert_fail.zip
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