There are resistor networks RN1 and RN3 between the FPGA and the '45 level shifters of the io ports. My guess is that these are there mostly to protect against the pins burning out due to contention when buggy hdl code is loaded.

If that is the reason, then it would only be consistent to add a resistor between the FPGA and the level shifter for the sync pin too.

Regarding the resistor value:
The value should most probably be the same as RN1 and RN3. But currently these are still marked as "TBD".

The current datasheet for the ice40hx doesn't specify a abs max. value for the io ports anymore. But on IRC daveshah found an old version of the datasheet that specifies 20mA:
http://static6.arrow.com/aropdfconversion/5439a9fe06e5510518bbd9887f93dff8a029b60a/ice40hxdatasheet120330.pdf
His guess is that this value got lost during the transition from SiliconBlue to Lattice.

20mA @ 3.3V would mean 165 Ohms. But the '45 would most probably drop the voltage on contention. So my guess is that 100 Ohms could be enough to protect from permanent damage, but 220 Ohms would be on the safe side.