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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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  • 1 commit
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Commits on May 15, 2019

  1. hdl.ir: when adding sync domain to a design, also add it to ports. 

    Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
    whitequark committed May 15, 2019
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