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Recent changes mean that the clk and reset signals are not exported to the inputs of the modules in examples
$ python ctr.py generate ctr.v
module top(o); wire [16:0] \$1 ; wire [16:0] \$2 ; (* src = "ctr.py:8" *) reg \$next\o ; (* src = "ctr.py:7" *) reg [15:0] \$next\v ; (* src = "/usr/local/lib/python3.7/dist-packages/nmigen-0.1-py3.7.egg/nmigen/hdl/ir.py:330" *) wire clk; (* src = "ctr.py:8" *) output o; (* src = "/usr/local/lib/python3.7/dist-packages/nmigen-0.1-py3.7.egg/nmigen/hdl/ir.py:330" *) wire rst; (* init = 16'hffff *) (* src = "ctr.py:7" *)
The clock and reset are wires rather than inputs to the module.
The text was updated successfully, but these errors were encountered:
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Recent changes mean that the clk and reset signals are not exported to the inputs of the modules
in examples
The clock and reset are wires rather than inputs to the module.
The text was updated successfully, but these errors were encountered: