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Hirarchy of submodules is not obvious from verilog #54

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anuejn opened this issue Mar 31, 2019 · 4 comments
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Hirarchy of submodules is not obvious from verilog #54

anuejn opened this issue Mar 31, 2019 · 4 comments
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backend:RTLIL improvement
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0.1

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@anuejn
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anuejn commented Mar 31, 2019

When adding a submodule to a submodule, the hirarchy is not obvious from the generated verilog.

Given the first submodule is named parent and its child child, I would suggest to name the verilog submodule for the child parent__child instead of child only.

What do you think?
@whitequark
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This would seriously mess up presentation in gtkwave, making it almost completely unreadable.

Maybe an attribute called nmigen.path? I.e. (* nmigen.path = "parent/child" *) as an addition to the current naming.

@anuejn
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anuejn commented Apr 1, 2019

Hm... that would be an option but not that nice imho.
maybe we should consider to fix gtkwave than for that use case.

@whitequark
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Sure, but gtkwave needs to be fixed first.

@whitequark
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I've added an attribute. I don't think anything else can be done here without breaking gtkwave (or without gtkwave being fixed).

@whitequark whitequark added this to the 0.1 milestone Jun 28, 2019
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