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When adding a submodule to a submodule, the hirarchy is not obvious from the generated verilog.
Given the first submodule is named parent and its child child, I would suggest to name the verilog submodule for the child parent__child instead of child only.
What do you think?
The text was updated successfully, but these errors were encountered:
When adding a submodule to a submodule, the hirarchy is not obvious from the generated verilog.
Given the first submodule is named
parent
and its childchild
, I would suggest to name the verilog submodule for the childparent__child
instead ofchild
only.What do you think?
The text was updated successfully, but these errors were encountered: