Creating signals named like verilog keywords produces invalid verilog #53

anuejn · 2019-03-31T21:05:53Z

The following valid migen code...

from nmigen import *
from nmigen.cli import main


input = Signal()
output = Signal()

m = Module()
m.d.comb += output.eq(input)

main(m, ports=[input, output])

... produces the following invalid verilog (with python fail.py generate:

/* Generated by Yosys 0.8+143 (git sha1 c82aa49d, gcc 8.2.1 -march=x86-64 -mtune=generic -O2 -fno-plt -fPIC -Os) */

(* top =  1  *)
(* generator = "nMigen" *)
module top(output, input);
  (* src = "fail.py:6" *)
  reg \$next\output ;
  (* src = "fail.py:5" *)
  input input;
  (* src = "fail.py:6" *)
  output output;
  always @* begin
    \$next\output  = 1'h0;
    \$next\output  = input;
  end
  assign output = \$next\output ;
endmodule

I dont really know, whether this should be handled by yosys (since nMigen produces valid ir) or by nMigen itself.

The text was updated successfully, but these errors were encountered:

programmerjake · 2019-03-31T21:32:48Z

I would think this is a yosys bug.

whitequark · 2019-03-31T22:56:11Z

You are using the Yosys commit just before I fixed that bug.

anuejn · 2019-04-01T14:25:15Z

ah thanks for fixing :), works now 👍

whitequark added the upstream label Mar 31, 2019

anuejn closed this as completed Apr 1, 2019

mithro mentioned this issue Apr 1, 2019

Should nMigen check Yosys version? #55

Closed

whitequark added duplicate and removed upstream labels Jun 28, 2019

This was referenced Jan 27, 2020

Creating signals named like verilog keywords produces invalid verilog amaranth-lang/amaranth#60

Closed

Should nMigen check Yosys version? amaranth-lang/amaranth#62

Closed

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Creating signals named like verilog keywords produces invalid verilog #53

Creating signals named like verilog keywords produces invalid verilog #53

anuejn commented Mar 31, 2019

programmerjake commented Mar 31, 2019

whitequark commented Mar 31, 2019

anuejn commented Apr 1, 2019

Creating signals named like verilog keywords produces invalid verilog #53

Creating signals named like verilog keywords produces invalid verilog #53

Comments

anuejn commented Mar 31, 2019

programmerjake commented Mar 31, 2019

whitequark commented Mar 31, 2019

anuejn commented Apr 1, 2019