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Neither comments nor defines are possible because Yosys' write_verilog cannot emit them arbitrarily. It's not even possible to add an attribute to an inner case, although it can be done on the always block.
I think that without Yosys modifications (which will probably have a hard time being accepted upstream) it's only really possible to set an attribute on the state signal, but this doesn't help a whole lot.
Currently when using an FSM, the generate Verilog looks something like;
If would be nice if the states in the case statement had some type of comment or other annotation which signified their names.
Using something like comments;
Using something like defines;
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