Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add FSM state name annotations to generated Verilog output #134

Closed
mithro opened this issue Jul 7, 2019 · 5 comments
Closed

Add FSM state name annotations to generated Verilog output #134

mithro opened this issue Jul 7, 2019 · 5 comments
Labels
backend:verilog improvement
Milestone
0.1

Comments

@mithro
Copy link

mithro commented Jul 7, 2019

Currently when using an FSM, the generate Verilog looks something like;

  always @* begin
    \current_word$next  = current_word;
    casez (fsm_state)
      2'h0:            
          /* empty */;
      2'h1:                  
        begin          
          \current_word$next [0] = io_miso[0];
          \current_word$next [1] = io_miso[1];
          \current_word$next [2] = io_miso[2];
          \current_word$next [3] = io_miso[3];
          \current_word$next [4] = io_miso[4];
          \current_word$next [5] = io_miso[5];
          \current_word$next [6] = io_miso[6];
          \current_word$next [7] = io_miso[7];
        end                  
      2'h2:            
        begin                     
          \current_word$next [4] = io_miso[0];
          \current_word$next [5] = io_miso[1];
          \current_word$next [6] = io_miso[2];
          \current_word$next [7] = io_miso[3];
        end
      2'h3:            
        begin    
          \current_word$next [6] = io_miso[0];
          \current_word$next [7] = io_miso[1];
        end                       
    endcase               
    casez (rst)                               
      1'h1:            
          \current_word$next  = 8'h00;
    endcase
  end

If would be nice if the states in the case statement had some type of comment or other annotation which signified their names.

Using something like comments;

  always @* begin
    \current_word$next  = current_word;
    casez (fsm_state)
      2'h0:            /* IDLE */
          /* empty */;
      2'h1:            /* SPI_x8 */      
        begin          
          \current_word$next [0] = io_miso[0];
          \current_word$next [1] = io_miso[1];
          \current_word$next [2] = io_miso[2];
          \current_word$next [3] = io_miso[3];
          \current_word$next [4] = io_miso[4];
          \current_word$next [5] = io_miso[5];
          \current_word$next [6] = io_miso[6];
          \current_word$next [7] = io_miso[7];
        end                  
      2'h2:            /* SPI_x4 */      
        begin                     
          \current_word$next [4] = io_miso[0];
          \current_word$next [5] = io_miso[1];
          \current_word$next [6] = io_miso[2];
          \current_word$next [7] = io_miso[3];
        end
      2'h3:            /* SPI_x2 */      
        begin    
          \current_word$next [6] = io_miso[0];
          \current_word$next [7] = io_miso[1];
        end                       
    endcase               
    casez (rst)                               
      1'h1:            
          \current_word$next  = 8'h00;
    endcase
  end

Using something like defines;

`define IDLE   2'h0
`define SPI_x8   2'h1
`define SPI_x4   2'h2
`define SPI_x2   2'h3

  always @* begin
    \current_word$next  = current_word;
    casez (fsm_state)
      IDLE:
          /* empty */;
      SPI_x8:
        begin          
          \current_word$next [0] = io_miso[0];
          \current_word$next [1] = io_miso[1];
          \current_word$next [2] = io_miso[2];
          \current_word$next [3] = io_miso[3];
          \current_word$next [4] = io_miso[4];
          \current_word$next [5] = io_miso[5];
          \current_word$next [6] = io_miso[6];
          \current_word$next [7] = io_miso[7];
        end                  
      SPI_x4:
        begin                     
          \current_word$next [4] = io_miso[0];
          \current_word$next [5] = io_miso[1];
          \current_word$next [6] = io_miso[2];
          \current_word$next [7] = io_miso[3];
        end
      SPI_x2:
        begin    
          \current_word$next [6] = io_miso[0];
          \current_word$next [7] = io_miso[1];
        end                       
    endcase               
    casez (rst)                               
      1'h1:            
          \current_word$next  = 8'h00;
    endcase
  end
@whitequark
Copy link
Contributor

Neither comments nor defines are possible because Yosys' write_verilog cannot emit them arbitrarily. It's not even possible to add an attribute to an inner case, although it can be done on the always block.

I think that without Yosys modifications (which will probably have a hard time being accepted upstream) it's only really possible to set an attribute on the state signal, but this doesn't help a whole lot.

@whitequark
Copy link
Contributor

@mithro Clifford is on board with this change.

@mithro
Copy link
Author

mithro commented Jul 8, 2019

Awesome! I look forward to seeing it work.

@whitequark
Copy link
Contributor

The Yosys part is done, and it will be in Yosys 0.9 as well.

@mithro
Copy link
Author

mithro commented Jul 9, 2019

@whitequark - You truly are my hero!

@whitequark whitequark added this to the 0.1 milestone Jul 10, 2019
Closed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
backend:verilog improvement
Projects
None yet
Milestone
0.1
Development

No branches or pull requests
2 participants
@mithro @whitequark