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base repository: m-labs/nmigen
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jul 7, 2019

  1. vendor.xilinx_7series: generate also binary bitfile.

    Fixes #139.
    peteut authored and whitequark committed Jul 7, 2019
    Copy the full SHA
    31c54d3 View commit details
Showing with 3 additions and 2 deletions.
  1. +3 −2 nmigen/vendor/xilinx_7series.py
5 changes: 3 additions & 2 deletions nmigen/vendor/xilinx_7series.py
Original file line number Diff line number Diff line change
@@ -42,7 +42,8 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
* ``{{name}}_timing.rpt``: Vivado report.
* ``{{name}}_power.rpt``: Vivado report.
* ``{{name}}_route.dcp``: Vivado design checkpoint.
* ``{{name}}.bit``: binary bitstream.
* ``{{name}}.bit``: binary bitstream with metadata.
* ``{{name}}.bin``: binary bitstream.
"""

toolchain = "Vivado"
@@ -92,7 +93,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
report_power -file {{name}}_power.rpt
{{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
write_bitstream -force {{name}}.bit
write_bitstream -force -bin_file {{name}}.bit
{{get_override("script_after_bitstream")|default("# (script_after_bitstream placeholder)")}}
quit
""",