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base repository: m-labs/nmigen
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Jun 11, 2019

  1. back.pysim: check for a clock being added twice.

    This commit adds a best-effort error for a common mistake of adding
    a clock driving the same domain twice, such as a result of
    a copy-paste error.
    
    Fixes #27.
    whitequark committed Jun 11, 2019
    Copy the full SHA
    066dd79 View commit details
Showing with 12 additions and 0 deletions.
  1. +5 −0 nmigen/back/pysim.py
  2. +7 −0 nmigen/test/test_sim.py
5 changes: 5 additions & 0 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -366,6 +366,7 @@ def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
self._delta = 0.
self._epsilon = 1e-10
self._fastest_clock = self._epsilon
self._all_clocks = set() # {str/domain}
self._state = _State()

self._processes = set() # {process}
@@ -426,6 +427,9 @@ def sync_process():
def add_clock(self, period, phase=None, domain="sync"):
if self._fastest_clock == self._epsilon or period < self._fastest_clock:
self._fastest_clock = period
if domain in self._all_clocks:
raise ValueError("Domain '{}' already has a clock driving it"
.format(domain))

half_period = period / 2
if phase is None:
@@ -440,6 +444,7 @@ def clk_process():
yield clk.eq(0)
yield Delay(half_period)
self.add_process(clk_process)
self._all_clocks.add(domain)

def __enter__(self):
if self._vcd_file:
7 changes: 7 additions & 0 deletions nmigen/test/test_sim.py
Original file line number Diff line number Diff line change
@@ -388,6 +388,13 @@ def test_add_process_wrong(self):
"a generator function"):
sim.add_process(1)

def test_add_clock_wrong(self):
with self.assertSimulation(Module()) as sim:
sim.add_clock(1)
with self.assertRaises(ValueError,
msg="Domain 'sync' already has a clock driving it"):
sim.add_clock(1)

def test_eq_signal_unused_wrong(self):
self.setUp_lhs_rhs()
self.s = Signal()