vendor.lattice_ecp5: add Diamond support. (WIP)

m-labs · Aug 20, 2019 · 274f279 · 274f279
1 parent 5ad409e
commit 274f279
Showing 1 changed file with 109 additions and 5 deletions.
diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
@@ -9,6 +9,9 @@
 
 class LatticeECP5Platform(TemplatedPlatform):
     """
+    Trellis toolchain
+    -----------------
+
     Required tools:
         * ``yosys``
         * ``nextpnr-ecp5``
@@ -34,14 +37,36 @@ class LatticeECP5Platform(TemplatedPlatform):
         * ``{{name}}.config``: ASCII bitstream.
         * ``{{name}}.bit``: binary bitstream.
         * ``{{name}}.svf``: JTAG programming vector.
+
+    Diamond toolchain
+    -----------------
+
+    Required tools:
+        * ``pnmainc``
+
+    The environment is populated by running the script specified in the environment variable
+    ``NMIGEN_Diamond_env``, if present. The script included with Diamond is not sufficient;
+    it is recommended to put another script named ``nmigen_diamond_env`` in the Diamond binary
+    directory with the following contents: ::
+
+        export bindir=$(dirname $0)
+        source $bindir/diamond_env
+
+    Available overrides:
+        * TODO
+
+    Build products:
+        * TODO
     """
 
-    toolchain = "Trellis"
+    toolchain = None # selected in initializer
 
     device  = abstractproperty()
     package = abstractproperty()
     speed   = abstractproperty()
 
+    # Trellis templates
+
     _nextpnr_device_options = {
         "LFE5U-12F":    "--25k",
         "LFE5U-25F":    "--25k",
@@ -64,7 +89,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         "BG756": "caBGA756",
     }
 
-    file_templates = {
+    _trellis_file_templates = {
         **TemplatedPlatform.build_script_templates,
         "{{name}}.il": r"""
             # {{autogenerated}}
@@ -98,7 +123,7 @@ class LatticeECP5Platform(TemplatedPlatform):
             {% endfor %}
         """
     }
-    command_templates = [
+    _trellis_command_templates = [
         r"""
         {{get_tool("yosys")}}
             {{quiet("-q")}}
@@ -127,6 +152,85 @@ class LatticeECP5Platform(TemplatedPlatform):
         """
     ]
 
+    # Diamond templates
+
+    _diamond_file_templates = {
+        **TemplatedPlatform.build_script_templates,
+        "{{name}}.v": r"""
+            /* {{autogenerated}} */
+            {{emit_design("verilog")}}
+        """,
+        "{{name}}.tcl": r"""
+        prj_project new -name "{{name}}" -impl "impl" -impl_dir "top_impl" \
+            -dev {{platform.device}}-{{platform.speed}}{{platform.package}}C \
+            -lpf "{{name}}.lpf" \
+            -synthesis synplify
+        {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            prj_src add "{{file}}"
+        {% endfor %}
+        prj_src add "{{name}}.v"
+        prj_impl option top "{{name}}"
+        prj_src add "{{name}}.sdc"
+        prj_project save
+        prj_run Synthesis -impl "impl" -forceAll
+        prj_run Translate -impl "impl" -forceAll
+        prj_run Map -impl "impl" -forceAll
+        prj_run PAR -impl "impl" -forceAll
+        prj_run Export -impl "impl" -forceAll -task Bitgen
+        """,
+        "{{name}}.lpf": r"""
+            # {{autogenerated}}
+            BLOCK ASYNCPATHS;
+            BLOCK RESETPATHS;
+            {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
+                LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
+                IOBUF PORT "{{port_name}}"
+                    {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
+            {% endfor %}
+        """,
+        "{{name}}.sdc": r"""
+            {% for signal, frequency in platform.iter_clock_constraints() -%}
+                create_clock -period {{1000000000/frequency}} [get_ports {{signal.name}}]
+            {% endfor %}
+        """,
+    }
+    _diamond_command_templates = [
+        r"""
+        {{get_tool("pnmainc")}} {{name}}.tcl
+        """,
+    ]
+
+    # Common logic
+
+    def __init__(self, toolchain="Diamond"):
+        super().__init__()
+        assert toolchain in ("Trellis", "Diamond")
+        self.toolchain = toolchain
+
+    @property
+    def file_templates(self):
+        if self.toolchain == "Trellis":
+            return self._trellis_file_templates
+        if self.toolchain == "Diamond":
+            return self._diamond_file_templates
+        assert False
+
+    @property
+    def command_templates(self):
+        if self.toolchain == "Trellis":
+            return self._trellis_command_templates
+        if self.toolchain == "Diamond":
+            return self._diamond_command_templates
+        assert False
+
+    @property
+    def unix_interpreter(self):
+        if self.toolchain == "Trellis":
+            return "sh"
+        if self.toolchain == "Diamond":
+            return "bash"
+        assert False
+
     def create_missing_domain(self, name):
         # No additional reset logic needed.
         return super().create_missing_domain(name)
@@ -194,7 +298,7 @@ def get_ixor(z, invert):
                 a = Signal.like(z, name_suffix="_x{}".format(1 if invert else 0))
                 for bit in range(len(z)):
                     m.submodules += Instance("LUT4",
-                        p_INIT=0x5555 if invert else 0xaaaa,
+                        p_INIT=Const(0x5555 if invert else 0xaaaa, 16),
                         i_A=a[bit],
                         i_B=Const(0),
                         i_C=Const(0),
@@ -210,7 +314,7 @@ def get_oxor(a, invert):
                 z = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
                 for bit in range(len(a)):
                     m.submodules += Instance("LUT4",
-                        p_INIT=0x5555 if invert else 0xaaaa,
+                        p_INIT=Const(0x5555 if invert else 0xaaaa, 16),
                         i_A=a[bit],
                         i_B=Const(0),
                         i_C=Const(0),