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base repository: GlasgowEmbedded/glasgow
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head repository: GlasgowEmbedded/glasgow
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compare: baf512e94c95
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Aug 19, 2019

  1. applet.audio.yamaha_opl: overclock less. 

    Overclocking OPL2 to 15 MHz doesn't seem to work that well.
    @whitequark
    whitequark committed Aug 19, 2019
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    82a59e8 View commit details

  2. Remove a stray copy of versioneer.

    @whitequark
    whitequark committed Aug 19, 2019
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    ca626bc View commit details

Commits on Aug 20, 2019

  1. README: expand acknowledgements.

    @whitequark
    whitequark committed Aug 20, 2019
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    baf512e View commit details
Showing with 2 additions and 1,823 deletions.
  1. +1 −0 README.md
  2. +1 −1 software/glasgow/applet/audio/yamaha_opl/__init__.py
  3. +0 −1,822 versioneer.py
1 change: 1 addition & 0 deletions README.md
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Original file line number Diff line number Diff line change
@@ -114,6 +114,7 @@ Although first-class Windows support is an important goal and Glasgow already wo
* [@marcan](https://github.com/marcan) improved almost every aspect of hardware for revC;
* [@esden](https://github.com/esden) is handling batch manufacturing;
* [@smunaut](https://github.com/smunaut) provided advice crucial for stability and performance of USB communication;
* [@electronic_eel](https://github.com/electronic_eel) designed the test jig and advanced protection circuitry;
* ... and many [other people](https://github.com/GlasgowEmbedded/Glasgow/graphs/contributors).

## License
2 changes: 1 addition & 1 deletion software/glasgow/applet/audio/yamaha_opl/__init__.py
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Original file line number Diff line number Diff line change
@@ -803,7 +803,7 @@ def build(self, target, args):
in_fifo=iface.get_in_fifo(depth=8192, auto_flush=False),
# It's useful to run the synthesizer at a frequency significantly higher than real-time
# to reduce the time spent waiting.
master_cyc=self.derive_clock(input_hz=target.sys_clk_freq, output_hz=15e6),
master_cyc=self.derive_clock(input_hz=target.sys_clk_freq, output_hz=8e6),
read_pulse_cyc=int(target.sys_clk_freq * 200e-9),
write_pulse_cyc=int(target.sys_clk_freq * 100e-9),
address_clocks=device_iface_cls.address_clocks,
1,822 changes: 0 additions & 1,822 deletions versioneer.py
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