Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/nmigen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 04c07715b41e
Choose a base ref
...
head repository: m-labs/nmigen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 3fc5f170e6a8
Choose a head ref
  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Jun 17, 2019

  1. vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.

    Before this commit, in some cases there will be an inverter, which is
    not allowed on an FDCE with IOB attribute set to true, as it will
    interfere with packing.
    whitequark committed Jun 17, 2019
    Copy the full SHA
    8b34602 View commit details
  2. vendor.xilinx_{7series,spartan6}: cleanup. NFC.

    Eliminate some intermediate signals if they are not necessary.
    Do not even return i, o, or t if the pin does not have them.
    whitequark committed Jun 17, 2019
    Copy the full SHA
    2a8e7bc View commit details
  3. vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.

    Do this to make sure all buffers, tristate/differential or not, are
    instantiated the exact same way, and are subject to the same set of
    toolchain bugs, if any.
    whitequark committed Jun 17, 2019
    Copy the full SHA
    3fc5f17 View commit details
Showing with 98 additions and 74 deletions.
  1. +8 −8 nmigen/vendor/lattice_ice40.py
  2. +45 −33 nmigen/vendor/xilinx_7series.py
  3. +45 −33 nmigen/vendor/xilinx_spartan6.py
16 changes: 8 additions & 8 deletions nmigen/vendor/lattice_ice40.py
Original file line number Diff line number Diff line change
@@ -129,7 +129,7 @@ def get_dff(clk, d, q):
i_D=d,
o_Q=q)

def get_i_inverter(y, invert):
def get_ixor(y, invert):
if invert is None:
return y
else:
@@ -144,7 +144,7 @@ def get_i_inverter(y, invert):
o_O=y[bit])
return a

def get_o_inverter(a, invert):
def get_oxor(a, invert):
if invert is None:
return a
else:
@@ -168,16 +168,16 @@ def get_o_inverter(a, invert):

if "i" in pin.dir:
if pin.xdr < 2:
pin_i = get_i_inverter(pin.i, i_invert)
pin_i = get_ixor(pin.i, i_invert)
elif pin.xdr == 2:
pin_i0 = get_i_inverter(pin.i0, i_invert)
pin_i1 = get_i_inverter(pin.i1, i_invert)
pin_i0 = get_ixor(pin.i0, i_invert)
pin_i1 = get_ixor(pin.i1, i_invert)
if "o" in pin.dir:
if pin.xdr < 2:
pin_o = get_o_inverter(pin.o, o_invert)
pin_o = get_oxor(pin.o, o_invert)
elif pin.xdr == 2:
pin_o0 = get_o_inverter(pin.o0, o_invert)
pin_o1 = get_o_inverter(pin.o1, o_invert)
pin_o0 = get_oxor(pin.o0, o_invert)
pin_o1 = get_oxor(pin.o1, o_invert)

if "i" in pin.dir and pin.xdr == 2:
i0_ff = Signal.like(pin_i0, name_suffix="_ff")
78 changes: 45 additions & 33 deletions nmigen/vendor/xilinx_7series.py
Original file line number Diff line number Diff line change
@@ -156,7 +156,7 @@ def get_oddr(clk, d1, d2, q):
o_Q=q[bit]
)

def get_i_inverter(y, invert):
def get_ixor(y, invert):
if invert is None:
return y
else:
@@ -169,7 +169,7 @@ def get_i_inverter(y, invert):
)
return a

def get_o_inverter(a, invert):
def get_oxor(a, invert):
if invert is None:
return a
else:
@@ -184,71 +184,83 @@ def get_o_inverter(a, invert):

if "i" in pin.dir:
if pin.xdr < 2:
pin_i = get_i_inverter(pin.i, i_invert)
pin_i = get_ixor(pin.i, i_invert)
elif pin.xdr == 2:
pin_i0 = get_i_inverter(pin.i0, i_invert)
pin_i1 = get_i_inverter(pin.i1, i_invert)
pin_i0 = get_ixor(pin.i0, i_invert)
pin_i1 = get_ixor(pin.i1, i_invert)
if "o" in pin.dir:
if pin.xdr < 2:
pin_o = get_o_inverter(pin.o, o_invert)
pin_o = get_oxor(pin.o, o_invert)
elif pin.xdr == 2:
pin_o0 = get_o_inverter(pin.o0, o_invert)
pin_o1 = get_o_inverter(pin.o1, o_invert)
pin_o0 = get_oxor(pin.o0, o_invert)
pin_o1 = get_oxor(pin.o1, o_invert)

i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
oe = Signal(1, name="{}_xdr_oe".format(pin.name))
i = o = t = None
if "i" in pin.dir:
i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
if "o" in pin.dir:
o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
if pin.dir in ("oe", "io"):
t = Signal(1, name="{}_xdr_t".format(pin.name))

if pin.xdr == 0:
if "i" in pin.dir:
m.d.comb += pin_i.eq(i)
i = pin_i
if "o" in pin.dir:
m.d.comb += o.eq(pin_o)
o = pin_o
if pin.dir in ("oe", "io"):
m.d.comb += oe.eq(pin.oe)
t = ~pin.oe
elif pin.xdr == 1:
if "i" in pin.dir:
get_dff(pin.i_clk, i, pin_i)
if "o" in pin.dir:
get_dff(pin.o_clk, pin_o, o)
if pin.dir in ("oe", "io"):
get_dff(pin.o_clk, pin.oe, oe)
get_dff(pin.o_clk, ~pin.oe, t)
elif pin.xdr == 2:
if "i" in pin.dir:
get_iddr(pin.i_clk, i, pin_i0, pin_i1)
if "o" in pin.dir:
get_oddr(pin.o_clk, pin_o0, pin_o1, o)
if pin.dir in ("oe", "io"):
get_dff(pin.o_clk, pin.oe, oe)
get_dff(pin.o_clk, ~pin.oe, t)
else:
assert False

return (i, o, oe)
return (i, o, t)

def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
i, o, oe = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
m.d.comb += i.eq(port)
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("IBUF",
i_I=port[bit],
o_O=i[bit]
)
return m

def get_output(self, pin, port, attrs, invert):
self._check_feature("single-ended output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
i, o, oe = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
m.d.comb += port.eq(o)
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("OBUF",
i_I=o[bit],
o_O=port[bit]
)
return m

def get_tristate(self, pin, port, attrs, invert):
self._check_feature("single-ended tristate", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
i, o, oe = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("OBUFT",
i_T=~oe,
i_T=t,
i_I=o[bit],
o_O=port[bit]
)
@@ -258,11 +270,11 @@ def get_input_output(self, pin, port, attrs, invert):
self._check_feature("single-ended input/output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
i, o, oe = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules += Instance("IOBUF",
i_T=~oe,
i_T=t,
i_I=o[bit],
o_O=i[bit],
io_IO=port[bit]
@@ -273,7 +285,7 @@ def get_diff_input(self, pin, p_port, n_port, attrs, invert):
self._check_feature("differential input", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
i, o, oe = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("IBUFDS",
i_I=p_port[bit], i_IB=n_port[bit],
@@ -285,7 +297,7 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
self._check_feature("differential output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
i, o, oe = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("OBUFDS",
i_I=o[bit],
@@ -297,10 +309,10 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
self._check_feature("differential tristate", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
i, o, oe = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("OBUFTDS",
i_T=~oe,
i_T=t,
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
)
@@ -310,11 +322,11 @@ def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
self._check_feature("differential input/output", pin, attrs,
valid_xdrs=(0, 1, 2), valid_attrs=True)
m = Module()
i, o, oe = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules += Instance("IOBUFDS",
i_T=~oe,
i_T=t,
i_I=o[bit],
o_O=i[bit],
io_IO=p_port[bit], io_IOB=n_port[bit]
Loading