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Make SYNC pullup smaller #51
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I think 300 Ohms is the lowest we can safely go. That'll give us 300 mV of rise above ground at 3.3V with 10 mA drivers. |
It's actually 24 mA. On the other hand, Vil(max) for LVCMOS 3.3 inputs is 0.8 V, so 0.3 V seems fine. |
Okay, that'd give us 125 Ohms. 130 for ease of sourcing. Math math math. |
Can you verify that this value actually gives a decent signal? I don't have my resistor set at hand... |
I have some 120 Ohm resistors, I can look at what those give. |
Hrm, I might have been looking at the wrong package. 300 mV rise seems pretty low too, that's not enough to sync using e.g. external LMVCMOS 3.3 circuitry... Let's aim at 800 mV rise above ground then. |
Because it's an open drain output, 300 mV is Vol in this case - the voltage for a logic 0. The high voltage will be the full VIO voltage. |
Oh right, I derped. That's fine then, let's go with 300 mV. |
The FPGA has ridiculously powerful drivers (what, 10 mA?) so if we use a pullup smaller than 1k we can go well into MHz range. Useful, because the PLL has a minimum frequency of 16 MHz--can we get that high?
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