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ESD protection on Vio and Vsense pins #59

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whitequark opened this issue May 21, 2018 · 2 comments
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ESD protection on Vio and Vsense pins #59

whitequark opened this issue May 21, 2018 · 2 comments
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hardware Component: hardware revB Hardware revision: B
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@whitequark
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FXMA108 gives us ESD protection on all I/O pins. However, what about the ADC and the LDO? In particular, the turned off LDO has the output in hi-Z state, which seems like it might have bad implications. Verify.
@whitequark whitequark added the revB Hardware revision: B label May 21, 2018
@whitequark whitequark added this to the Preview 1 milestone May 21, 2018
@awygle
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awygle commented May 22, 2018

The LDO has 2 kV ESD tolerance, the ADC has 2.5 kV (on the pins in question, under the human body model). The LDO rail has 4.7 uF of capacitance, and the ADC has 12 nF before the input pin. Given that the human body model specifies 200 pF of capacitance, we have an effective 250 kV of tolerance, which should be plenty.

See https://irclog.whitequark.org/~h~openfpga/2018-05-22#22149898; for discussion with @azonenberg on this topic.

@whitequark
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Agreed.

@whitequark whitequark added the hardware Component: hardware label Apr 16, 2019
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