Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: whitequark/Boneless-CPU
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: f1a113bd6e0e
Choose a base ref
...
head repository: whitequark/Boneless-CPU
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: f4051b5fd165
Choose a head ref
  • 4 commits
  • 4 files changed
  • 1 contributor

Commits on Jul 12, 2019

  1. gateware.decoder_v3: implement JAL. 

    Change: -1 LUT.

(Really???)
    @whitequark
    whitequark committed Jul 12, 2019
    Copy the full SHA
    9bdc785 View commit details

  2. arch.opcode_v3: design JALR.

    @whitequark
    whitequark committed Jul 12, 2019
    Copy the full SHA
    3b6535e View commit details

  3. gateware.{core,decoder}_v3: implement JALR. 

    Change: -12 LUT.

(Really?????)
    @whitequark
    whitequark committed Jul 12, 2019
    Copy the full SHA
    924663b View commit details

  4. gateware.{core,decoder}_v3: implement JT. (all implemented now!) 

    Change: +15 LUT.

(This just loses what we've recently mysteriously gained. And it's
not even related to JT, just to general refactoring...)
    @whitequark
    whitequark committed Jul 12, 2019
    Copy the full SHA
    f4051b5 View commit details
Showing with 81 additions and 68 deletions.
  1. +3 −3 boneless/arch/opcode_v3.py
  2. +40 −41 boneless/gateware/core_v3.py
  3. +38 −24 boneless/gateware/decoder_v3.py
  4. BIN doc/design.ods
6 changes: 3 additions & 3 deletions boneless/arch/opcode_v3.py
View file
Original file line number Diff line number Diff line change
@@ -16,7 +16,7 @@
"LD", "LDR", "ST", "STR", "LDX", "LDXA", "STX", "STXA",
"MOVI", "MOVR",
"STW", "SWPW", "ADJW", "LDW",
"JR", "JV", "JT", "JAL",
"JR", "JALR", "JV", "JT", "JAL",
"JNZ", "JZ", "JNS", "JS", "JNC", "JC", "JNO", "JO", "JN", "J",
"JNE", "JE", "JULT", "JUGE", "JUGT", "JULE", "JSGE", "JSLT", "JSGT", "JSLE",
"EXTI"
@@ -75,7 +75,7 @@ class C_LDW (Instr): coding = "10100---011-----"

# Jump opcodes
class C_JR (Instr): coding = "10100---100-----"
# class C_? (Instr): coding = "10100---101-----"
class C_JALR (Instr): coding = "10100---101-----"
class C_JV (Instr): coding = "10100---110-----"
class C_JT (Instr): coding = "10100---111-----"; pc_rel_ops = {"imm"}
class C_JAL (Instr): coding = "10101-----------"; pc_rel_ops = {"imm"}
@@ -153,7 +153,7 @@ class LDW (C_LDW, F_R5 ): pass

# Jump instructions
class JR (C_JR, F_R5 ): pass
# class ? (C_?, F_R5 ): pass
class JALR(C_JALR, F_RR ): pass
class JV (C_JV, F_R5 ): pass
class JT (C_JT, F_R5 ): pass
class JAL (C_JAL, F_R8 ): pass
81 changes: 40 additions & 41 deletions boneless/gateware/core_v3.py
View file
Original file line number Diff line number Diff line change
@@ -106,6 +106,8 @@ def __init__(self):
self.c_op = self.Op.signal()
self.c_xbus = Signal()

self.r_xbus = Signal()

self.o_bus_addr = Signal(16)

self.i_mem_data = Signal(16)
@@ -136,6 +138,7 @@ def elaborate(self, platform):
m.d.comb += self.o_bus_addr.eq(Cat(self.i_rsd, self.i_w))
with m.Switch(op.dir):
with m.Case(self.MuxDir.RD):
m.d.sync += self.r_xbus.eq(0)
m.d.comb += self.o_mem_re.eq(1)
with m.Case(self.MuxDir.WR):
m.d.comb += self.o_mem_we.eq(1)
@@ -144,27 +147,20 @@ def elaborate(self, platform):
m.d.comb += self.o_bus_addr.eq(self.i_ptr)
with m.Switch(op.dir):
with m.Case(self.MuxDir.RD):
with m.If(~self.c_xbus):
m.d.comb += self.o_mem_re.eq(1)
with m.Else():
m.d.sync += self.r_xbus.eq(self.c_xbus)
with m.If(self.c_xbus):
m.d.comb += self.o_ext_re.eq(1)
with m.Case(self.MuxDir.WR):
with m.If(~self.c_xbus):
m.d.comb += self.o_mem_we.eq(1)
with m.Else():
m.d.comb += self.o_mem_re.eq(1)
with m.Case(self.MuxDir.WR):
with m.If(self.c_xbus):
m.d.comb += self.o_ext_we.eq(1)

r_mem_re = Signal()
r_ext_re = Signal()
m.d.sync += [
r_mem_re.eq(self.o_mem_re),
r_ext_re.eq(self.o_ext_re),
]
with m.Else():
m.d.comb += self.o_mem_we.eq(1)

m.d.comb += self.o_mem_data.eq(self.i_data)
m.d.comb += self.o_ext_data.eq(self.i_data)
m.d.comb += self.o_data.eq((Repl(r_mem_re, 16) & self.i_mem_data) |
(Repl(r_ext_re, 16) & self.i_ext_data))
m.d.comb += self.o_data.eq(Mux(self.r_xbus, self.i_ext_data, self.i_mem_data))

return m

@@ -177,6 +173,7 @@ def __init__(self, alsru_cls, reset_pc=0, reset_w=0xffff, memory=None):

self.r_insn = Signal(16)
self.s_base = Signal(16)
self.s_a = Signal(16)
self.r_a = Signal(16)
self.s_b = Signal(16)
self.s_f = Record(self.r_f.layout)
@@ -275,6 +272,23 @@ def elaborate(self, platform):
m_shift.i_shamt.eq(self.s_b),
]

with m.Switch(m_dec.o_ld_a):
with m.Case(m_dec.LdA.ZERO):
m.d.comb += self.s_a.eq(0)
with m.Case(m_dec.LdA.W):
m.d.comb += self.s_a.eq(self.r_w << 3)
with m.Case(m_dec.LdA.PCp1):
m.d.comb += self.s_a.eq(m_dec.o_pc_p1)
with m.Case(m_dec.LdX_PTR):
m.d.comb += self.s_a.eq(m_arb.o_data)
m.d.sync += self.r_a.eq(self.s_a)

with m.Switch(m_dec.o_ld_b):
with m.Case(m_dec.LdB.IMM):
m.d.comb += self.s_b.eq(m_dec.o_imm16)
with m.Case(m_dec.LdX_PTR):
m.d.comb += self.s_b.eq(m_arb.o_data)

with m.FSM():
m.d.comb += m_dec.i_insn.eq(self.r_insn)
m.d.comb += self.s_base.eq(self.r_a)
@@ -295,18 +309,9 @@ def elaborate(self, platform):
m.next = "LOAD-B"

with m.State("LOAD-B"):
with m.Switch(m_dec.o_ld_a):
with m.Case(m_dec.LdA.ZERO):
m.d.sync += self.r_a.eq(0)
with m.Case(m_dec.LdA.W):
m.d.sync += self.r_a.eq(self.r_w << 3)
with m.Case(m_dec.LdA.PCp1):
m.d.sync += self.r_a.eq(m_dec.o_pc_p1)
with m.Case(m_dec.LdX_PTR):
m.d.sync += self.r_a.eq(m_arb.o_data)
m.d.comb += self.s_base.eq(m_arb.o_data)
m.d.comb += self.s_base.eq(self.s_a)
with m.Switch(m_dec.o_ld_b):
with m.Case(m_dec.LdB.ApI):
with m.Case(m_dec.LdB.IND):
m.d.comb += m_arb.c_op.eq(m_arb.Op.LD_PTR)
with m.Case(m_dec.LdB.RSD):
m.d.comb += m_arb.c_op.eq(m_arb.Op.LD_RSD)
@@ -315,13 +320,16 @@ def elaborate(self, platform):
m.next = "EXECUTE"

with m.State("EXECUTE"):
with m.Switch(m_dec.o_ld_b):
with m.Case(m_dec.LdB.IMM):
m.d.comb += self.s_b.eq(m_dec.o_imm16)
with m.Case(m_dec.LdX_PTR):
m.d.comb += self.s_b.eq(m_arb.o_data)
with m.If(m_dec.o_shift):
m.d.comb += m_shift.c_en.eq(1)
m.d.comb += m_shift.c_load.eq(self.r_cycle == 0)
m.d.comb += self.o_done.eq(m_shift.o_done)
with m.Elif(m_dec.o_multi):
m.d.comb += self.o_done.eq(self.r_cycle == 1)
with m.Else():
m.d.comb += self.o_done.eq(1)
with m.Switch(m_dec.o_st_r):
with m.Case(m_dec.StR.ApI):
with m.Case(m_dec.StR.IND):
m.d.comb += m_arb.c_op.eq(m_arb.Op.ST_PTR)
with m.Case(m_dec.StR.RSD):
m.d.comb += m_arb.c_op.eq(m_arb.Op.ST_RSD)
@@ -338,15 +346,6 @@ def elaborate(self, platform):
m.d.sync += self.r_pc.eq(m_alsru.o)
with m.Else():
m.d.sync += self.r_pc.eq(m_dec.o_pc_p1)
with m.If(m_dec.o_shift):
m.d.comb += m_shift.c_en.eq(1)
m.d.comb += m_shift.c_load.eq(self.r_cycle == 0)
m.d.comb += self.o_done.eq(m_shift.o_done)
with m.Elif(m_dec.o_multi):
m.d.comb += self.o_done.eq(self.r_cycle == 1)
with m.Else():
m.d.comb += self.o_done.eq(1)
with m.If(self.o_done):
m.d.sync += self.r_cycle.eq(0)
m.next = "FETCH"
with m.Else():
62 changes: 38 additions & 24 deletions boneless/gateware/decoder_v3.py
View file
Original file line number Diff line number Diff line change
@@ -82,13 +82,13 @@ class LdA(ControlEnum):

class LdB(ControlEnum):
IMM = 0b0_11
ApI = 0b1_00
IND = 0b1_00
RSD = 0b1_01
RB = 0b1_11

class StR(ControlEnum):
x = 0b0_00
ApI = 0b1_00
IND = 0b1_00
RSD = 0b1_01

class StF(ControlEnum):
@@ -314,7 +314,7 @@ def elaborate(self, platform):
self.o_op.eq(alsru_cls.Op.SR),
]
with m.If(self.c_cycle == 0):
m.d.comb += self.o_op.eq(alsru_cls.Op.A)
m.d.comb += self.o_op.eq(alsru_cls.Op.A) # overrides above

with m.Case(opcode.C_LD.coding, opcode.C_ST.coding):
m.d.comb += [
@@ -330,13 +330,13 @@ def elaborate(self, platform):
with m.Switch(self.i_insn):
with m.Case(opcode.C_LD.coding):
m.d.comb += [
self.o_ld_b.eq(self.LdB.ApI),
self.o_ld_b.eq(self.LdB.IND),
self.o_st_r.eq(self.StR.RSD),
]
with m.Case(opcode.C_ST.coding):
m.d.comb += [
self.o_ld_b.eq(self.LdB.RSD),
self.o_st_r.eq(self.StR.ApI),
self.o_st_r.eq(self.StR.IND),
]

with m.Case(opcode.C_LDX.coding, opcode.C_STX.coding):
@@ -348,23 +348,23 @@ def elaborate(self, platform):
with m.Case(opcode.M_ABS.coding):
m.d.comb += [
m_imm.c_width.eq(m_imm.Width.IMM5),
self.o_ld_a.eq(self.LdA.RA)
self.o_ld_a.eq(self.LdA.RA),
]
with m.Case(opcode.M_LIT.coding):
m.d.comb += [
m_imm.c_width.eq(m_imm.Width.IMM8),
self.o_ld_a.eq(self.LdA.ZERO)
self.o_ld_a.eq(self.LdA.ZERO),
]
with m.Switch(self.i_insn):
with m.Case(opcode.C_LDX.coding):
m.d.comb += [
self.o_ld_b.eq(self.LdB.ApI),
self.o_ld_b.eq(self.LdB.IND),
self.o_st_r.eq(self.StR.RSD),
]
with m.Case(opcode.C_STX.coding):
m.d.comb += [
self.o_ld_b.eq(self.LdB.RSD),
self.o_st_r.eq(self.StR.ApI),
self.o_st_r.eq(self.StR.IND),
]

with m.Case(opcode.C_MOVE.coding):
@@ -412,14 +412,10 @@ def elaborate(self, platform):
self.o_st_r.eq(self.StR.RSD),
]
with m.If(self.c_cycle == 0):
m.d.comb += [
self.o_st_w.eq(1),
self.o_st_r.eq(self.StR.x),
]
with m.Else():
m.d.comb += [
self.o_op.eq(alsru_cls.Op.A),
]
m.d.comb += self.o_st_w.eq(1)
m.d.comb += self.o_st_r.eq(self.StR.x) # overrides above
with m.If(self.c_cycle == 1):
m.d.comb += self.o_op.eq(alsru_cls.Op.A) # overrides above

with m.Case(opcode.C_JR.coding):
m.d.comb += [
@@ -430,13 +426,25 @@ def elaborate(self, platform):
self.o_st_pc.eq(1),
]

# with m.Case(opcode.C_J?.coding):
with m.Case(opcode.C_JALR.coding):
m.d.comb += [
m_imm.c_width.eq(m_imm.Width.IMM5), # unused, simplifies decoding
self.o_multi.eq(1),
self.o_ld_a.eq(self.LdA.PCp1),
self.o_ld_b.eq(self.LdB.RB),
self.o_st_pc.eq(1),
]
with m.If(self.c_cycle == 0):
m.d.comb += self.o_op.eq(alsru_cls.Op.A)
m.d.comb += self.o_st_r.eq(self.StR.RSD)
with m.If(self.c_cycle == 1):
m.d.comb += self.o_op.eq(alsru_cls.Op.B)

with m.Case(opcode.C_JV.coding):
m.d.comb += [
m_imm.c_width.eq(m_imm.Width.IMM5),
self.o_ld_a.eq(self.LdA.RSD),
self.o_ld_b.eq(self.LdB.ApI),
self.o_ld_b.eq(self.LdB.IND),
self.o_op.eq(alsru_cls.Op.ApB),
self.o_st_pc.eq(1),
]
@@ -446,30 +454,36 @@ def elaborate(self, platform):
m_imm.c_width.eq(m_imm.Width.IMM5),
m_imm.c_pcrel.eq(1),
self.o_multi.eq(1),
self.o_ld_a.eq(self.LdA.RSD),
self.o_ld_b.eq(self.LdB.ApI),
self.o_ld_a.eq(self.LdA.RSD), # latches [M] on 2nd cycle
self.o_op.eq(alsru_cls.Op.ApB),
self.o_st_pc.eq(1),
]
with m.If(self.c_cycle == 0):
m.d.comb += self.o_ld_b.eq(self.LdB.IND)
with m.If(self.c_cycle == 1):
m.d.comb += self.o_ld_b.eq(self.LdB.IMM)

with m.Case(opcode.C_JAL.coding):
m.d.comb += [
m_imm.c_width.eq(m_imm.Width.IMM8),
self.o_multi.eq(1),
self.o_ld_a.eq(self.LdA.PCp1),
self.o_ld_b.eq(self.LdB.IMM),
self.o_op.eq(alsru_cls.Op.ApB),
self.o_st_r.eq(self.StR.RSD),
self.o_st_pc.eq(1),
]
with m.If(self.c_cycle == 0):
m.d.comb += self.o_op.eq(alsru_cls.Op.A)
m.d.comb += self.o_st_r.eq(self.StR.RSD)
with m.If(self.c_cycle == 1):
m.d.comb += self.o_op.eq(alsru_cls.Op.ApB)

with m.Case(opcode.C_JCOND.coding):
m.d.comb += [
m_imm.c_width.eq(m_imm.Width.IMM8),
self.o_jcc.eq(1),
self.o_ld_a.eq(self.LdA.PCp1),
self.o_ld_b.eq(self.LdB.IMM),
self.o_op.eq(alsru_cls.Op.A), # not taken
self.o_op.eq(alsru_cls.Op.A), # overridden in core if taken
self.o_st_pc.eq(1),
]

Binary file modified doc/design.ods
View file
Binary file not shown.