whitequark · Jul 13, 2019
diff --git a/boneless/arch/opcode.py b/boneless/arch/opcode.py
@@ -15,8 +15,8 @@
     "SLL",  "SLLI", "ROT",  "ROTI", "SRL",  "SRLI", "SRA",  "SRAI",
     "LD",   "LDR",  "ST",   "STR",  "LDX",  "LDXA", "STX",  "STXA",
     "MOVI", "MOVR",
-    "STW",  "SWPW", "ADJW", "LDW",
-    "JR",   "JALR", "JV",   "JT",   "JAL",
+    "STW",  "XCHW", "ADJW", "LDW",
+    "JR",   "JRAL", "JVT",  "JST",  "JAL",
     "JNZ",  "JZ",   "JNS",  "JS",   "JNC",  "JC",   "JNO",  "JO",   "JN",   "J",
     "JNE",  "JE",   "JULT", "JUGE", "JUGT", "JULE", "JSGE", "JSLT", "JSGT", "JSLE",
     "EXTI"
@@ -69,15 +69,15 @@ class C_MOVE (Instr): coding = "1000------------"
 
 # Window opcodes
 class C_STW  (Instr): coding = "10100---000-----"
-class C_SWPW (Instr): coding = "10100---001-----"
+class C_XCHW (Instr): coding = "10100---001-----"
 class C_ADJW (Instr): coding = "10100---010-----"
 class C_LDW  (Instr): coding = "10100---011-----"
 
 # Jump opcodes
 class C_JR   (Instr): coding = "10100---100-----"
-class C_JALR (Instr): coding = "10100---101-----"
-class C_JV   (Instr): coding = "10100---110-----"
-class C_JT   (Instr): coding = "10100---111-----"; pc_rel_ops = {"imm"}
+class C_JRAL (Instr): coding = "10100---101-----"
+class C_JVT  (Instr): coding = "10100---110-----"
+class C_JST  (Instr): coding = "10100---111-----"; pc_rel_ops = {"imm"}
 class C_JAL  (Instr): coding = "10101-----------"; pc_rel_ops = {"imm"}
 
 # Conditional opcode
@@ -147,15 +147,15 @@ class MOVR(C_MOVE,  M_REL,          F_R8  ): pass
 
 # Window instructions
 class STW (C_STW,                   F_XR  ): pass
-class SWPW(C_SWPW,                  F_RR  ): pass
+class XCHW(C_XCHW,                  F_RR  ): pass
 class ADJW(C_ADJW,                  F_X5  ): pass
 class LDW (C_LDW,                   F_R5  ): pass
 
 # Jump instructions
 class JR  (C_JR,                    F_R5  ): pass
-class JALR(C_JALR,                  F_RR  ): pass
-class JV  (C_JV,                    F_R5  ): pass
-class JT  (C_JT,                    F_R5  ): pass
+class JRAL(C_JRAL,                  F_RR  ): pass
+class JVT (C_JVT,                   F_R5  ): pass
+class JST (C_JST,                   F_R5  ): pass
 class JAL (C_JAL,                   F_R8  ): pass
 
 # Conditional instructions

diff --git a/boneless/gateware/decoder.py b/boneless/gateware/decoder.py
@@ -381,7 +381,7 @@ def elaborate(self, platform):
                     self.o_st_r.eq(self.StR.RSD),
                 ]
 
-            with m.Case(opcode.C_STW.coding,  opcode.C_SWPW.coding,
+            with m.Case(opcode.C_STW.coding,  opcode.C_XCHW.coding,
                         opcode.C_ADJW.coding, opcode.C_LDW.coding):
                 m.d.comb += [
                     m_imm.c_width.eq(m_imm.Width.IMM5),
@@ -394,7 +394,7 @@ def elaborate(self, platform):
                             self.o_ld_b.eq(self.LdB.RB),
                             self.o_op.eq(alsru_cls.Op.B),
                         ]
-                    with m.Case(opcode.C_SWPW.coding):
+                    with m.Case(opcode.C_XCHW.coding):
                         m.d.comb += [
                             self.o_ld_b.eq(self.LdB.RB),
                             self.o_op.eq(alsru_cls.Op.B),
@@ -426,7 +426,7 @@ def elaborate(self, platform):
                     self.o_st_pc.eq(1),
                 ]
 
-            with m.Case(opcode.C_JALR.coding):
+            with m.Case(opcode.C_JRAL.coding):
                 m.d.comb += [
                     m_imm.c_width.eq(m_imm.Width.IMM5), # unused, simplifies decoding
                     self.o_multi.eq(1),
@@ -440,7 +440,7 @@ def elaborate(self, platform):
                 with m.If(self.c_cycle == 1):
                     m.d.comb += self.o_op.eq(alsru_cls.Op.B)
 
-            with m.Case(opcode.C_JV.coding):
+            with m.Case(opcode.C_JVT.coding):
                 m.d.comb += [
                     m_imm.c_width.eq(m_imm.Width.IMM5),
                     self.o_ld_a.eq(self.LdA.RSD),
@@ -449,7 +449,7 @@ def elaborate(self, platform):
                     self.o_st_pc.eq(1),
                 ]
 
-            with m.Case(opcode.C_JT.coding):
+            with m.Case(opcode.C_JST.coding):
                 m.d.comb += [
                     m_imm.c_width.eq(m_imm.Width.IMM5),
                     m_imm.c_pcrel.eq(1),

diff --git a/boneless/test/smoke.py b/boneless/test/smoke.py
@@ -313,11 +313,11 @@ def test_STW(self):
         yield from self.assertW(0x1230)
 
     @simulation_test
-    def test_SWPW(self):
+    def test_XCHW(self):
         yield from self.execute(
             regs=[0x0010],
             code=[STW (R0),
-                  SWPW(R0, R0)],
+                  XCHW(R0, R0)],
             data=[0, 0, 0, 0, 0, 0,
                   0x0018, 0, 0, 0, 0, 0, 0, 0,
                   0, 0, 0, 0, 0, 0, 0, 0])
@@ -351,26 +351,26 @@ def test_JR(self):
         yield from self.assertPC(0x1234 + 2)
 
     @simulation_test
-    def test_JALR(self):
+    def test_JRAL(self):
         yield from self.execute(
             regs=[0x1234, 0],
-            code=[JALR(R1, R0)])
+            code=[JRAL(R1, R0)])
         yield from self.assertPC(0x1234)
         yield from self.assertMemory(1, 9)
 
     @simulation_test
-    def test_JV(self):
+    def test_JVT(self):
         yield from self.execute(
             regs=[0x0009],
-            code=[JV  (R0, 1)],
+            code=[JVT (R0, 1)],
             data=[0x1234, 0x5678])
         yield from self.assertPC(0x0009 + 0x5678)
 
     @simulation_test
-    def test_JT(self):
+    def test_JST(self):
         yield from self.execute(
             regs=[0x0001],
-            code=[JT  (R0, 2)],
+            code=[JST (R0, 2)],
             data=[0, 0, 0x1234, 0x5678])
         yield from self.assertPC(9 + 2 + 0x5678)
 

diff --git a/doc/design.ods b/doc/design.ods
diff --git a/doc/manual/insns/ADC.tex b/doc/manual/insns/ADC.tex
@@ -6,12 +6,12 @@
   \purpose{To add 16-bit integers in registers, with carry input.}
   \restrictions{None.}
   \begin{operation}\aluRR{opA + opB + C}\wb\flagZSCV\end{operation}
-  \begin{remarks}
-  A 32-bit addition with both operands in registers can be performed as follows:
-  \begin{alltt}
-  ; Perform (R1|R0) ← (R3|R2) + (R5|R4)
-  ADD  R0, R2, R4
-  ADC  R1, R3, R5
-  \end{alltt}
-  \end{remarks}
+\begin{remarks}
+A 32-bit addition with both operands in registers can be performed as follows:
+\begin{alltt}
+; Perform (R1|R0) ← (R3|R2) + (R5|R4)
+    ADD  R0, R2, R4
+    ADC  R1, R3, R5
+\end{alltt}
+\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/ADCI.tex b/doc/manual/insns/ADCI.tex
@@ -9,13 +9,13 @@
   \assembly{\mnemonic{} Rd, Ra, imm}
   \purpose{To add a constant to a 16-bit integer in a register, with carry input.}
   \restrictions{None.}
-  \begin{operation}\aluRI{opA + opB + C}\wb\flagZSCV\end{operation}
-  \begin{remarks}
-  A 32-bit addition with a register and an immediate operand can be performed as follows:
-  \begin{alltt}
-  ; Perform (R1|R0) ← (R3|R2) + 0x40001
-  ADDI R0, R2, 1
-  ADCI R1, R3, 4
-  \end{alltt}
-  \end{remarks}
+  \begin{operation}\aluRI{al}{opA + opB + C}\wb\flagZSCV\end{operation}
+\begin{remarks}
+A 32-bit addition with a register and an immediate operand can be performed as follows:
+\begin{alltt}
+; Perform (R1|R0) ← (R3|R2) + 0x40001
+    ADDI R0, R2, 1
+    ADCI R1, R3, 4
+\end{alltt}
+\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/ADDI.tex b/doc/manual/insns/ADDI.tex
@@ -9,5 +9,5 @@
   \assembly{\mnemonic{} Rd, Ra, imm}
   \purpose{To add a constant to a 16-bit integer in a register.}
   \restrictions{None.}
-  \begin{operation}\aluRI{opA + opB}\wb\flagZSCV\end{operation}
+  \begin{operation}\aluRI{al}{opA + opB}\wb\flagZSCV\end{operation}
 \end{instruction}
diff --git a/doc/manual/insns/ADJW.1.tex b/doc/manual/insns/ADJW.1.tex
diff --git a/doc/manual/insns/ADJW.2.tex b/doc/manual/insns/ADJW.2.tex
diff --git a/doc/manual/insns/ADJW.tex b/doc/manual/insns/ADJW.tex
@@ -0,0 +1,17 @@
+\begin{instruction}{ADJW}{Adjust Window Address}
+  \begin{encoding*}{short}
+    \mnemonic & \op{5}{10100} & \opx{3}{000} & \op{3}{010} & \imm{5} \\
+  \end{encoding*}
+  \begin{encoding*}{long}
+    \exti
+    \mnemonic & \op{5}{10100} & \opx{3}{000} & \op{3}{010} & \imm{5} \\
+  \end{encoding*}
+  \assembly{\mnemonic{} imm}
+  \purpose{To increase or decrease the address of the register window.}
+  \restrictions{If \texttt{imm} contains a value that is not a multiple of 8, the behavior is \unpredictable. If the long form is used, and \texttt{imm5[4:3]} are non-zero, the behavior is \unpredictable.}
+\begin{operation}\imm{5}
+W ← W + imm
+\end{operation}
+  \begin{remarks}This instruction may be used in a function prologue or epilogue.\end{remarks}
+  \begin{notice}The interpretation of the immediate field of this instruction is not final.\end{notice}
+\end{instruction}
diff --git a/doc/manual/insns/ANDI.tex b/doc/manual/insns/ANDI.tex
@@ -7,7 +7,7 @@
     \mnemonic & \op{5}{00001} & \reg{d} & \reg{a} & \op{2}{00} & \imm{3} \\
   \end{encoding*}
   \assembly{\mnemonic{} Rd, Ra, imm}
-  \purpose{To perform bitwise AND between a constant and a 16-bit integer in a register.}
+  \purpose{To perform bitwise AND between a 16-bit integer in a register and a constant.}
   \restrictions{None.}
-  \begin{operation}\aluRI{opA \K{and} opB}\wb\flagZS\end{operation}
+  \begin{operation}\aluRI{al}{opA \K{and} opB}\wb\flagZS\end{operation}
 \end{instruction}
diff --git a/doc/manual/insns/CMP.tex b/doc/manual/insns/CMP.tex
@@ -6,5 +6,5 @@
   \purpose{To compare 16-bit integers in registers.}
   \restrictions{None.}
   \begin{operation}\aluRR{opA - opB}\flagZSBV\end{operation}
-  \begin{remarks}This instruction is identical to \texttt{SUB}, with the exception that it discards the computed value.\end{remarks}
+  \begin{remarks}This instruction behaves identically to \texttt{SUB}, with the exception that it discards the computed value.\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/CMPI.tex b/doc/manual/insns/CMPI.tex
@@ -1,14 +1,14 @@
 \begin{instruction}{CMPI}{Compare to Immediate}
   \begin{encoding*}{short}
-    \mnemonic & \op{5}{00001} & \op{3}{000} & \reg{a} & \op{2}{11} & \imm{3} \\
+    \mnemonic & \op{5}{00001} & \opx{3}{000} & \reg{a} & \op{2}{11} & \imm{3} \\
   \end{encoding*}
   \begin{encoding*}{long}
     \exti
-    \mnemonic & \op{5}{00001} & \op{3}{000} & \reg{a} & \op{2}{11} & \imm{3} \\
+    \mnemonic & \op{5}{00001} & \opx{3}{000} & \reg{a} & \op{2}{11} & \imm{3} \\
   \end{encoding*}
   \assembly{\mnemonic{} Rd, Ra, imm}
   \purpose{To compare a constant to a 16-bit integer in a register.}
   \restrictions{None.}
-  \begin{operation}\aluRI{opA - opB}\flagZSBV\end{operation}
-  \begin{remarks}This instruction is identical to \texttt{SUBI}, with the exception that it discards the computed value.\end{remarks}
+  \begin{operation}\aluRI{al}{opA - opB}\flagZSBV\end{operation}
+  \begin{remarks}This instruction behaves identically to \texttt{SUBI}, with the exception that it discards the computed value.\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/ENTR.tex b/doc/manual/insns/ENTR.tex
diff --git a/doc/manual/insns/EXTI.tex b/doc/manual/insns/EXTI.tex
@@ -2,12 +2,12 @@
   \begin{encoding}
     \mnemonic & \op{3}{110} & \imm{13} \\
   \end{encoding}
-  \assembly{\mnemonic{} Rd, Ra, Rb}
-  \purpose{To extend the range of immediate in the next executed instruction.}
+  \assembly{\mnemonic{} imm}
+  \purpose{To extend the range of immediate in the following instruction.}
   \restrictions{None.}
 \begin{operation}
 ext13 ← imm13
-has_ext13 ← 1
+has\_ext13 ← 1
 \end{operation}
-  \begin{remarks}This instruction is exclusively emitted by the assembler while translating other instructions. As it changes both the meaning of and the constraints placed on the immediate field in the following instruction, the assembler does not accept a mnemonic for \texttt{EXTI}.\end{remarks}
+  \begin{remarks}This instruction is automatically emitted by the assembler while translating other instructions. As it changes both the meaning of and the constraints placed on the immediate field in the following instruction, placing it manually may lead to unexpected results.\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/J.tex b/doc/manual/insns/J.tex
@@ -8,6 +8,6 @@
   \end{encoding*}
   \assembly{\mnemonic{} label}
   \purpose{To unconditionally transfer control.}
-  \input{jump-restrictions.tex}
+  \input{off8-restrictions.tex}
   \begin{operation}\off{8}PC ← PC + 1 + off\end{operation}
 \end{instruction}
diff --git a/doc/manual/insns/JAL.tex b/doc/manual/insns/JAL.tex
@@ -1,4 +1,4 @@
-\begin{instruction}{JAL}{Jump And Link}
+\begin{instruction}{JAL}{Jump and Link}
   \begin{encoding*}{short}
     \mnemonic & \op{5}{10101} & \reg{d} & \off{8} \\
   \end{encoding*}
@@ -8,9 +8,9 @@
   \end{encoding*}
   \assembly{\mnemonic{} label}
   \purpose{To transfer control to a subroutine.}
-  \input{jump-restrictions.tex}
-  \begin{operation}\off{8}
+  \input{off8-restrictions.tex}
+\begin{operation}\off{8}
 mem[W|Rd] ← PC + 1
 PC ← PC + 1 + off
-  \end{operation}
+\end{operation}
 \end{instruction}
diff --git a/doc/manual/insns/JC.tex b/doc/manual/insns/JC.tex
@@ -7,8 +7,8 @@
     \mnemonic & \op{4}{1011} & \op{4}{1010} & \off{8} \\
   \end{encoding*}
   \assembly{\mnemonic{} label}
-  \purpose{To transfer control if an arithmetic or shift operation resulted in unsigned overflow.}
-  \input{jump-restrictions.tex}
+  \purpose{To transfer control if an arithmetic operation resulted in unsigned overflow.}
+  \input{off8-restrictions.tex}
   \begin{operation}\off{8}\jump{C}\end{operation}
   \begin{remarks}This instruction has the same encoding as \insnref{JUGE}.\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/JE.tex b/doc/manual/insns/JE.tex
@@ -8,7 +8,7 @@
   \end{encoding*}
   \assembly{\mnemonic{} label}
   \purpose{To transfer control after a \texttt{\insnref{CMP} Ra, Rb} instruction if \texttt{Ra} is equal to \texttt{Rb}.}
-  \input{jump-restrictions.tex}
+  \input{off8-restrictions.tex}
   \begin{operation}\off{8}\jump{Z}\end{operation}
   \begin{remarks}This instruction has the same encoding as \insnref{JZ}.\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/JN.tex b/doc/manual/insns/JN.tex
@@ -8,7 +8,7 @@
   \end{encoding*}
   \assembly{\mnemonic{} label}
   \purpose{To serve as a placeholder for a jump instruction.}
-  \input{jump-restrictions.tex}
+  \input{off8-restrictions.tex}
   \begin{operation}PC ← PC + 1\end{operation}
-  \begin{remarks}The \texttt{JN} instruction has no effect. It may be used as a placeholder for a different jump instruction with a predefiend offset when the exact condition is unknown, such as in certain self-modifying code.\end{remarks}
+  \begin{remarks}The \texttt{JN} instruction has no effect. It may be used as a placeholder for a different jump instruction with a predefined offset when the exact condition is unknown, such as in certain self-modifying code.\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/JNC.tex b/doc/manual/insns/JNC.tex
@@ -7,8 +7,8 @@
     \mnemonic & \op{4}{1011} & \op{4}{0010} & \off{8} \\
   \end{encoding*}
   \assembly{\mnemonic{} label}
-  \purpose{To transfer control if an arithmetic or shift operation did not result in unsigned overflow.}
-  \input{jump-restrictions.tex}
+  \purpose{To transfer control if an arithmetic operation did not result in unsigned overflow.}
+  \input{off8-restrictions.tex}
   \begin{operation}\off{8}\jump{\K{not} C}\end{operation}
   \begin{remarks}This instruction has the same encoding as \insnref{JULT}.\end{remarks}
 \end{instruction}
diff --git a/doc/manual/insns/JNE.tex b/doc/manual/insns/JNE.tex
@@ -8,7 +8,7 @@
   \end{encoding*}
   \assembly{\mnemonic{} label}
   \purpose{To transfer control after a \texttt{\insnref{CMP} Ra, Rb} instruction if \texttt{Ra} is not equal to \texttt{Rb}.}
-  \input{jump-restrictions.tex}
+  \input{off8-restrictions.tex}
   \begin{operation}\off{8}\jump{\K{not} Z}\end{operation}
   \begin{remarks}This instruction has the same encoding as \insnref{JNZ}.\end{remarks}
 \end{instruction}