Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: GlasgowEmbedded/glasgow
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 43e6ffa7e8e0
Choose a base ref
...
head repository: GlasgowEmbedded/glasgow
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 68bd607f47f5
Choose a head ref
  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Mar 25, 2019

  1. Revert "gateware.fx2: re-register FX2 outputs. (UPDATE FIRMWARE.)" 

    This reverts commit 684e458.

That commit broke the audio-yamaha-opl3 applet *badly*. It is not
clear exactly what the issue is but the correct fix is likely to
stop relying on flags to detect a buffer full condition and instead
use a local counter on the FPGA side, and use flags only to detect
the out of buffers condition.
    @whitequark
    whitequark committed Mar 25, 2019
    Copy the full SHA
    68bd607 View commit details
Showing with 7 additions and 15 deletions.
  1. +1 −1 firmware/fifo.c
  2. +6 −14 software/glasgow/gateware/fx2.py
2 changes: 1 addition & 1 deletion firmware/fifo.c
View file
Original file line number Diff line number Diff line change
@@ -41,7 +41,7 @@ void fifo_init() {
}

#define OUT_THRESHOLD 1U
#define IN_THRESHOLD 509U
#define IN_THRESHOLD 510U

void fifo_configure(bool two_ep) {
uint8_t ep26buf, ep48valid, ep26pkts;
20 changes: 6 additions & 14 deletions software/glasgow/gateware/fx2.py
View file
Original file line number Diff line number Diff line change
@@ -105,6 +105,7 @@ def __init__(self, fifo, asynchronous=False, auto_flush=True):

class _RegisteredTristate(Module):
def __init__(self, io):

self.oe = Signal()
self.o = Signal.like(io)
self.i = Signal.like(io)
@@ -113,18 +114,6 @@ def get_bit(signal, bit):
return signal[bit] if signal.nbits > 0 else signal

for bit in range(io.nbits):
# The FX2 output valid window starts well after (5.4 ns past) the iCE40 input
# capture window for the rising edge. However, the input capture for
# the falling edge is just right.
#
# We carefully use DDR input and fabric registers to capture the FX2 output in
# the valid window and prolong its validity to 1 IFCLK cycle. The output is
# not DDR and is handled the straightforward way.
#
# See https://github.com/GlasgowEmbedded/Glasgow/issues/89 for details.

bit_r = Signal()
self.sync += get_bit(self.i, bit).eq(bit_r)
self.specials += \
Instance("SB_IO",
# PIN_INPUT_REGISTERED|PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
@@ -134,7 +123,11 @@ def get_bit(signal, bit):
i_INPUT_CLK=ClockSignal(),
i_OUTPUT_CLK=ClockSignal(),
i_D_OUT_0=get_bit(self.o, bit),
o_D_IN_1=bit_r,
# The FX2 output valid window starts well after (5.4 ns past) the iCE40 input
# capture window for the rising edge. However, the input capture for
# the falling edge is just right.
# See https://github.com/GlasgowEmbedded/Glasgow/issues/89 for details.
o_D_IN_1=get_bit(self.i, bit),
)


@@ -236,7 +229,6 @@ def do_finalize(self):
If(addr[1],
NextState("SETUP-IN")
).Else(
slrd.eq(1),
NextState("SETUP-OUT")
)
)