This makes clear the limitations of the current SERDES engine (i.e.
that the maximum clock rate is 1/4 of applet clock) and handles edge
conditions reliably. It could also enable higher rates in the future.

This allows us greater freedom in changing the latency of the FX2
arbiter for IN and OUT transfers alike.

This is a fairly significant change that could lead to corruption of
data in transit and hangs, but it seems OK based on testing with
the following applets:
  * benchmark
  * memory-25x
  * video-rgb-input

Also, gruetzkopf has verified this according to documentation and
silicon behavior and it also appears fully equivalent.

Before this commit, the FX2 arbiter would incorrectly use FX2 outputs
in the fabric that were actually only valid for 1/2 of IFCLK period,
because they were DDR input signals. After this commit, these signals
are correctly re-registered in fabric so that they are valid for
an entire IFCLK period, increasing latency by one cycle.

Fixes #89.

This means that frame skip is detected correctly but the subtarget is
still completely reset and starts from frame 0.

Something changed in Yosys and/or nextpnr and now they look for
the constraint on por_clk, not sys_clk, and silently ignore the one
on sys_clk. We need to fix that as well sometime...

This reverts commit 684e458.

That commit broke the audio-yamaha-opl3 applet *badly*. It is not
clear exactly what the issue is but the correct fix is likely to
stop relying on flags to detect a buffer full condition and instead
use a local counter on the FPGA side, and use flags only to detect
the out of buffers condition.

This also makes the applet more efficient by performing the unsigned-
to-signed conversion with numpy, or avoiding a roundtrip, in case
libsamplerate is used.