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base repository: GlasgowEmbedded/glasgow
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head repository: GlasgowEmbedded/glasgow
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compare: 0a64301d2df7
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jul 31, 2019

  1. applet.interface.jtag_probe: add {exchange,read}_ir methods. 

    These are occasionally useful if the Capture-IR state loads the bits
with some state information, e.g. Xilinx FPGAs put DONE, INIT, etc
values there.
    @whitequark
    whitequark committed Jul 31, 2019
    Copy the full SHA
    0a64301 View commit details
Showing with 39 additions and 6 deletions.
  1. +39 −6 software/glasgow/applet/interface/jtag_probe/__init__.py
45 changes: 39 additions & 6 deletions software/glasgow/applet/interface/jtag_probe/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -418,13 +418,27 @@ async def run_test_idle(self, count):
await self.enter_run_test_idle()
await self.pulse_tck(count)

async def write_ir(self, data):
async def exchange_ir(self, data):
self._current_ir = data = bitarray(data, endian="little")
self._log_h("exchange ir")
await self.enter_shift_ir()
data = await self.shift_tdio(data)
await self.enter_update_ir()
return data

async def read_ir(self, count):
self._current_ir = bitarray("1", endian="little") * count
await self.enter_shift_ir()
data = await self.shift_tdo(count)
await self.enter_update_ir()
self._log_h("read ir=<%s>", data.to01())
return data

async def write_ir(self, data, elide=True):
if data == self._current_ir:
self._log_h("write ir (elided)")
return
else:
self._current_ir = bitarray(data, endian="little")

self._current_ir = data = bitarray(data, endian="little")
self._log_h("write ir=<%s>", data.to01())
await self.enter_shift_ir()
await self.shift_tdi(data)
@@ -452,6 +466,7 @@ async def read_dr(self, count, idempotent=False):
return data

async def write_dr(self, data):
data = bitarray(data, endian="little")
self._log_h("write dr=<%s>", data.to01())
await self.enter_shift_dr()
await self.shift_tdi(data)
@@ -598,14 +613,15 @@ def affix(offset, length, total_length):
suffix = bypass * (total_length - offset - length)
return prefix, suffix

return TAPInterface(self,
return TAPInterface(self, ir_length,
*affix(ir_offset, ir_length, total_ir_length),
*affix(dr_offset, dr_length, total_dr_length))


class TAPInterface:
def __init__(self, lower, ir_prefix, ir_suffix, dr_prefix, dr_suffix):
def __init__(self, lower, ir_length, ir_prefix, ir_suffix, dr_prefix, dr_suffix):
self.lower = lower
self.ir_length = ir_length
self._ir_prefix = ir_prefix
self._ir_suffix = ir_suffix
self._ir_overhead = len(ir_prefix) + len(ir_suffix)
@@ -619,8 +635,25 @@ async def test_reset(self):
async def run_test_idle(self, count):
await self.lower.run_test_idle(count)

async def exchange_ir(self, data):
data = bitarray(data, endian="little")
assert len(data) == self.ir_length
data = await self.lower.exchange_ir(self._ir_prefix + data + self._ir_suffix)
if self._ir_suffix:
return data[len(self._ir_prefix):-len(self._ir_suffix)]
else:
return data[len(self._ir_prefix):]

async def read_ir(self):
data = await self.lower.read_ir(self._ir_overhead + self.ir_length)
if self._ir_suffix:
return data[len(self._ir_prefix):-len(self._ir_suffix)]
else:
return data[len(self._ir_prefix):]

async def write_ir(self, data):
data = bitarray(data, endian="little")
assert len(data) == self.ir_length
await self.lower.write_ir(self._ir_prefix + data + self._ir_suffix)

async def exchange_dr(self, data):