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base repository: GlasgowEmbedded/glasgow
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head repository: GlasgowEmbedded/glasgow
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compare: 8ce5b1183ce1
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Jul 29, 2019

  1. Verified

    This commit was signed with the committer’s verified signature.
    dariakp Daria Pardue
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    52c880a View commit details
  2. applet.memory.{24x,25x}: improve pinout diagrams.

    We can do much better now that we have the :: formatting directive.
    whitequark committed Jul 29, 2019

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    dariakp Daria Pardue
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    8ce5b11 View commit details
Showing with 17 additions and 7 deletions.
  1. +6 −4 software/glasgow/applet/memory/_24x/__init__.py
  2. +10 −2 software/glasgow/applet/memory/_25x/__init__.py
  3. +1 −1 software/glasgow/support/pyrepl.py
10 changes: 6 additions & 4 deletions software/glasgow/applet/memory/_24x/__init__.py
Original file line number Diff line number Diff line change
@@ -100,11 +100,13 @@ class Memory24xApplet(I2CMasterApplet, name="memory-24x"):
Conversely, specifying a larger page size, when applicable, will significantly improve write
performance.
# Pinout
The pinout of a typical 24-series IC is as follows (the A2:0 pins may be N/C in large devices):
The pinout of a typical 24-series IC is as follows:
* 8-pin: A0=1 A1=2 A2=3 SDA=5 SCL=6 WP=7 VCC=8 GND=4
::
A0 @ * VCC
A1 * * WP#
A2 * * SCL
GND * * SDA
""".format(page_size=default_page_size)

@classmethod
12 changes: 10 additions & 2 deletions software/glasgow/applet/memory/_25x/__init__.py
Original file line number Diff line number Diff line change
@@ -226,8 +226,16 @@ class Memory25xApplet(SPIMasterApplet, name="memory-25x"):
The pinout of a typical 25-series IC is as follows:
* 8-pin: SS#=1 MISO=2 MOSI=5 SCK=6 HOLD#=7 VCC=8 GND=4
* 16-pin: SS#=7 MISO=8 MOSI=15 SCK=16 HOLD#=1 VCC=2 GND=10
::
16-pin 8-pin
HOLD# @ * SCK SS# @ * VCC
VCC * * MOSI MISO * * HOLD#
N/C * * N/C WP# * * SCK
N/C * * N/C GND * * MOSI
N/C * * N/C
N/C * * N/C
SS# * * GND
MISO * * WP#
"""

@classmethod
2 changes: 1 addition & 1 deletion software/glasgow/support/pyrepl.py
Original file line number Diff line number Diff line change
@@ -49,7 +49,7 @@ def runcode(self, code):
async def interact(self):
while True:
try:
super().interact(banner="")
super().interact(banner="", exitmsg="")
break
except _FutureResult:
self.resetbuffer()