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base repository: GlasgowEmbedded/glasgow
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base: 96216948ae57
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head repository: GlasgowEmbedded/glasgow
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compare: 96568aaa59d4
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  • 1 commit
  • 3 files changed
  • 1 contributor

Commits on Aug 7, 2019

  1. Commit missing parts of 1639a25.

    @whitequark
    whitequark committed Aug 7, 2019
    Copy the full SHA
    96568aa View commit details
4 changes: 2 additions & 2 deletions software/glasgow/applet/interface/spi_master/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -327,7 +327,7 @@ def build(self, target, args, pins=__pins):
out_fifo=iface.get_out_fifo(),
in_fifo=iface.get_in_fifo(auto_flush=False),
period_cyc=self.derive_clock(input_hz=target.sys_clk_freq,
output_hz=args.bit_rate * 1000,
output_hz=args.frequency * 1000,
clock_name="master",
# 2 cyc MultiReg delay from SCK to MISO requires a 4 cyc
# period with current implementation of SERDES
@@ -373,7 +373,7 @@ def setup_loopback(self):
@applet_simulation_test("setup_loopback",
["--pin-sck", "0", "--pin-ss", "1",
"--pin-mosi", "2", "--pin-miso", "3",
"--bit-rate", "5000"])
"--frequency", "5000"])
@asyncio.coroutine
def test_loopback(self):
mux_iface = self.applet.mux_interface
6 changes: 3 additions & 3 deletions software/glasgow/applet/program/avr/spi.py
View file
Original file line number Diff line number Diff line change
@@ -245,16 +245,16 @@ def add_build_arguments(cls, parser, access):
access.add_pin_argument(parser, "mosi", default=True)

parser.add_argument(
"-b", "--bit-rate", metavar="FREQ", type=int, default=100,
help="set SPI bit rate to FREQ kHz (default: %(default)s)")
"-f", "--frequency", metavar="FREQ", type=int, default=100,
help="set SPI frequency to FREQ kHz (default: %(default)s)")

def build(self, target, args):
self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
subtarget = iface.add_subtarget(SPIMasterSubtarget(
pads=iface.get_pads(args, pins=self.__pins),
out_fifo=iface.get_out_fifo(),
in_fifo=iface.get_in_fifo(auto_flush=False),
period_cyc=math.ceil(target.sys_clk_freq / (args.bit_rate * 1000)),
period_cyc=math.ceil(target.sys_clk_freq / (args.frequency * 1000)),
delay_cyc=math.ceil(target.sys_clk_freq / 1e6),
sck_idle=0,
sck_edge="rising",
6 changes: 3 additions & 3 deletions software/glasgow/applet/program/nrf24l/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -151,8 +151,8 @@ def add_build_arguments(cls, parser, access):
access.add_pin_argument(parser, "reset", default=True)

parser.add_argument(
"-b", "--bit-rate", metavar="FREQ", type=int, default=1000,
help="set SPI bit rate to FREQ kHz (default: %(default)s)")
"-f", "--frequency", metavar="FREQ", type=int, default=1000,
help="set SPI frequency to FREQ kHz (default: %(default)s)")

def build(self, target, args):
dut_prog, self.__addr_dut_prog = target.registers.add_rw(1)
@@ -165,7 +165,7 @@ def build(self, target, args):
pads=pads,
out_fifo=iface.get_out_fifo(),
in_fifo=iface.get_in_fifo(auto_flush=True),
period_cyc=math.ceil(target.sys_clk_freq / (args.bit_rate * 1000)),
period_cyc=math.ceil(target.sys_clk_freq / (args.frequency * 1000)),
delay_cyc=math.ceil(target.sys_clk_freq / 1e6),
sck_idle=0,
sck_edge="rising",