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base repository: GlasgowEmbedded/glasgow
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base: 00591df2244c
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head repository: GlasgowEmbedded/glasgow
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compare: c2b99cc00ea9
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Aug 7, 2019

  1. applet.audio.dac: prevent sampling clock drift due to divider error.

    @whitequark
    whitequark committed Aug 7, 2019
    Copy the full SHA
    c2b99cc View commit details
Showing with 8 additions and 3 deletions.
  1. +8 −3 software/glasgow/applet/audio/dac/__init__.py
11 changes: 8 additions & 3 deletions software/glasgow/applet/audio/dac/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -164,13 +164,18 @@ def build(self, target, args):
if args.frequency is None:
pulse_cyc = 0
else:
pulse_cyc = self.derive_clock(input_hz=target.sys_clk_freq,
output_hz=args.frequency * 1e6)
pulse_cyc = self.derive_clock(clock_name="modulation",
input_hz=target.sys_clk_freq, output_hz=args.frequency * 1e6)
sample_cyc = self.derive_clock(clock_name="sampling",
input_hz=target.sys_clk_freq, output_hz=args.sample_rate,
# Drift of sampling clock is extremely bad, so ensure it only happens insofar as
# the oscillator on the board is imprecise, and with no additional error.
max_deviation_ppm=0)
subtarget = iface.add_subtarget(AudioDACSubtarget(
pads=iface.get_pads(args, pin_sets=self.__pin_sets),
out_fifo=iface.get_out_fifo(),
pulse_cyc=pulse_cyc,
sample_cyc=int(target.sys_clk_freq // args.sample_rate),
sample_cyc=sample_cyc,
width=args.width,
signed=args.signed,
))