GlasgowEmbedded · Aug 6, 2019 · Aug 6, 2019 · Aug 6, 2019
Showing with 27 additions and 8 deletions.

+14 −3 software/glasgow/access/direct/arguments.py

+2 −2 software/glasgow/applet/interface/spi_master/__init__.py

+11 −3 software/glasgow/applet/memory/_25x/__init__.py
diff --git a/software/glasgow/access/direct/arguments.py b/software/glasgow/access/direct/arguments.py
@@ -38,20 +38,31 @@ def _add_port_voltage_arguments(self, parser, default):
             "--keep-voltage", action="store_true", default=False,
             help="do not change I/O port voltage")
 
-    def _pin_number(self, arg):
+    def _mandatory_pin_number(self, arg):
         if not re.match(r"^[0-9]+$", arg):
             self._arg_error("{} is not a valid pin number", arg)
         return int(arg)
 
+    def _optional_pin_number(self, arg):
+        if arg == "-":
+            return None
+        return self._mandatory_pin_number(arg)
+
     def _add_pin_argument(self, parser, name, default, required):
         help = "bind the applet I/O line {!r} to pin NUM".format(name)
         if default is not None:
             help += " (default: %(default)s)"
 
+        if required:
+            type = self._mandatory_pin_number
+            if default is not None:
+                required = False
+        else:
+            type = self._optional_pin_number
+
         opt_name = "--pin-" + name.lower().replace("_", "-")
         parser.add_argument(
-            opt_name, metavar="NUM", type=self._pin_number, default=default, required=required,
-            help=help)
+            opt_name, metavar="NUM", type=type, default=default, required=required, help=help)
 
     def _pin_set(self, width, arg):
         if re.match(r"^[0-9]+:[0-9]+$", arg):

diff --git a/software/glasgow/applet/interface/spi_master/__init__.py b/software/glasgow/applet/interface/spi_master/__init__.py
@@ -307,8 +307,8 @@ def add_build_arguments(cls, parser, access, omit_pins=False):
             access.add_pin_argument(parser, "miso")
 
         parser.add_argument(
-            "-b", "--bit-rate", metavar="FREQ", type=int, default=100,
-            help="set SPI bit rate to FREQ kHz (default: %(default)s)")
+            "-f", "--frequency", metavar="FREQ", type=int, default=100,
+            help="set SPI clock frequency to FREQ kHz (default: %(default)s)")
         parser.add_argument(
             "--sck-idle", metavar="LEVEL", type=int, choices=[0, 1], default=0,
             help="set idle clock level to LEVEL (default: %(default)s)")

diff --git a/software/glasgow/applet/memory/_25x/__init__.py b/software/glasgow/applet/memory/_25x/__init__.py
@@ -236,13 +236,21 @@ class Memory25xApplet(SPIMasterApplet, name="memory-25x"):
           N/C * * N/C
           SS# * * GND
          MISO * * WP#
+
+    The default pin assignment follows the pinouts above in the clockwise direction, making it easy
+    to connect the memory with probes or, alternatively, crimp an IDC cable wired to a SOIC clip.
     """
 
     @classmethod
     def add_build_arguments(cls, parser, access):
-        super().add_build_arguments(parser, access)
-
-        access.add_pin_argument(parser, "hold")
+        super().add_build_arguments(parser, access, omit_pins=True)
+
+        access.add_pin_argument(parser, "ss",   default=True, required=True)
+        access.add_pin_argument(parser, "miso", default=True, required=True)
+        access.add_pin_argument(parser, "wp",   default=True)
+        access.add_pin_argument(parser, "mosi", default=True, required=True)
+        access.add_pin_argument(parser, "sck",  default=True, required=True)
+        access.add_pin_argument(parser, "hold", default=True)
 
     def build(self, target, args):
         subtarget = super().build(target, args)