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base repository: m-labs/nmigen
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base: 6ee760e83fc8
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head repository: m-labs/nmigen
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compare: ee15538cf01c
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jul 12, 2019

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    ee15538 View commit details
Showing with 1 addition and 1 deletion.
  1. +1 −1 nmigen/back/pysim.py
2 changes: 1 addition & 1 deletion nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -849,7 +849,7 @@ def __exit__(self, *args):
def add_trace(signal, **kwargs):
signal_slot = self._signal_slots[signal]
if self._vcd_names[signal_slot] is not None:
if len(signal) > 1:
if len(signal) > 1 and not signal.decoder:
suffix = "[{}:0]".format(len(signal) - 1)
else:
suffix = ""