whitequark · Jul 10, 2019 · Jul 10, 2019 · Jul 10, 2019
Showing with 15 additions and 4 deletions.

+6 −3 boneless/gateware/core_v3.py

+9 −1 boneless/gateware/decoder_v3.py
diff --git a/boneless/gateware/core_v3.py b/boneless/gateware/core_v3.py
@@ -110,16 +110,18 @@ def elaborate(self, platform):
 
 
 class CoreFSM(Elaboratable):
-    def __init__(self, alsru_cls, memory=None):
-        self.r_pc    = Signal(16)
-        self.r_w     = Signal(13)
+    def __init__(self, alsru_cls, reset_pc=0, reset_w=0xffff, memory=None):
+        self.r_pc    = Signal(16, reset=reset_pc)
+        self.r_w     = Signal(13, reset=reset_w >> 3)
         self.r_f     = Record([("z", 1), ("s", 1), ("c", 1), ("v", 1)])
 
         self.r_insn  = Signal(16)
         self.r_a     = Signal(16)
         self.s_b     = Signal(16)
         self.s_f     = Record(self.r_f.layout)
 
+        self.o_done  = Signal()
+
         self.m_dec   = InstructionDecoder(alsru_cls)
         self.m_arb   = BusArbiter()
         self.m_alsru = alsru_cls(width=16)
@@ -249,6 +251,7 @@ def elaborate(self, platform):
                     m.d.sync += self.r_w .eq(m_alsru.o >> 3)
                 with m.If(m_dec.o_jump):
                     m.d.sync += self.r_pc.eq(m_alsru.o)
+                m.d.comb += self.o_done.eq(1)
                 m.next = "FETCH"
 
         return m

diff --git a/boneless/gateware/decoder_v3.py b/boneless/gateware/decoder_v3.py
@@ -114,11 +114,19 @@ class Cond(ControlEnum):
         SxVoZ = 0b110
         A     = 0b111
 
+    @staticmethod
+    def _insn_decoder(encoding):
+        try:
+            insn = opcode.Instr.from_int(encoding)
+            return str(insn).expandtabs(1)
+        except ValueError:
+            return "{:04x}".format(encoding)
+
     def __init__(self, alsru_cls):
         self.alsru_cls = alsru_cls
 
         self.i_pc    = Signal(16)
-        self.i_insn  = Signal(16)
+        self.i_insn  = Signal(16, decoder=self._insn_decoder)
 
         self.o_pc_p1 = Signal(16)
         self.o_imm16 = Signal(16)