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tracer.get_var_name returns None instead of default on pypy3 #141
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I don't think that's the right solution because this way, with PyPy, you cannot generate meaningful Verilog at all. You'd think simulation would be much faster on PyPy, but I've evaluated it in the past (with a workaround for this issue), and it is significantly slower than on CPython. Since PyPy's bytecode is quite similar to CPython's, the right solution here is to not hack around it but to implement proper support for PyPy bytecode. Because of its slowness I do not think it currently makes any sense to put effort into it, but if you are interested in PyPy I would accept a patch that does that and add it to Travis' build matrix. |
I've found pypy to be much slower at elaborating but much faster at simulation. As an example, running test_core.py in ieee754fpu, which tests part of a div/rem/fdiv/fsqrt/frsqrt pipeline, it takes about 930s using pypy3 (7.2.0-beta0) and 1370s using python3 (3.6.8) on my Ryzen 2600. It tests about 140k simulated clock cycles. |
Interesting. I think the reason here is that the workloads are different. IIRC I benchmarked simulation on small cores, where it might be that the tracing JIT doesn't work as well. Anyway, that's good to know. In light of this information I think it is worthwhile to support PyPy as a first-class runtime. |
on pypy3 (pypy 7.2.0-beta0),
tracer.get_var_name
returnsNone
when called throughSignal.__init__
as follows:instead of returning
None
, it would be better to returndefault
or raise an exception.having
None
as the name causesSimulator
to crash.The text was updated successfully, but these errors were encountered: