whitequark · Jul 10, 2019 · Jul 10, 2019 · Jul 10, 2019
Showing with 25 additions and 2 deletions.

+2 −1 boneless/arch/instr_v3.py

+3 −1 boneless/gateware/core_v3.py

+10 −0 boneless/gateware/decoder_v3.py

+10 −0 boneless/test/test_instr_v3.py
diff --git a/boneless/arch/instr_v3.py b/boneless/arch/instr_v3.py
@@ -53,7 +53,8 @@ def prepare(cls, value):
 
     @property
     def is_legal(self):
-        return self.value in range(-1 << self.bits - 1, 1 << self.bits - 1)
+        return self.value & 0xffff not in range((+1 << self.bits - 1) & 0xffff,
+                                                (-1 << self.bits - 1) & 0xffff)
 
     @classmethod
     def from_str(cls, input):

diff --git a/boneless/gateware/core_v3.py b/boneless/gateware/core_v3.py
@@ -167,7 +167,6 @@ def elaborate(self, platform):
             m_arb.i_rsd.eq(m_dec.o_rsd),
             m_arb.i_ra .eq(m_dec.o_ra),
             m_arb.i_rb .eq(m_dec.o_rb),
-            m_arb.i_ptr.eq(m_dec.o_imm16 + self.r_a),
         ]
 
         m.submodules.alsru = m_alsru = self.m_alsru
@@ -198,6 +197,7 @@ def elaborate(self, platform):
             m.d.comb += m_dec.i_insn.eq(self.r_insn)
 
             with m.State("FETCH"):
+                m.d.comb += m_dec.c_done.eq(1)
                 m.d.sync += self.r_pc.eq(m_dec.o_pc_p1)
                 m.d.comb += m_arb.c_op.eq(m_arb.Op.LD_PC)
                 m.next = "LOAD-A"
@@ -222,6 +222,7 @@ def elaborate(self, platform):
                         m.d.sync += self.r_a.eq(m_arb.o_data)
                 with m.Switch(m_dec.o_ld_b):
                     with m.Case(m_dec.LdB.ApI):
+                        m.d.comb += m_arb.i_ptr.eq(self.m_arb.o_data + m_dec.o_imm16)
                         m.d.comb += m_arb.c_op.eq(
                             Mux(m_dec.o_xbus, m_arb.Op.LD_EXT, m_arb.Op.LD_MEM))
                     with m.Case(m_dec.LdB.RSD):
@@ -238,6 +239,7 @@ def elaborate(self, platform):
                         m.d.comb += self.s_b.eq(m_arb.o_data)
                 with m.Switch(m_dec.o_st_r):
                     with m.Case(m_dec.StR.ApI):
+                        m.d.comb += m_arb.i_ptr.eq(self.r_a + m_dec.o_imm16)
                         m.d.comb += m_arb.c_op.eq(
                             Mux(m_dec.o_xbus, m_arb.Op.ST_EXT, m_arb.Op.ST_MEM))
                     with m.Case(m_dec.StR.RSD):

diff --git a/boneless/gateware/decoder_v3.py b/boneless/gateware/decoder_v3.py
@@ -128,6 +128,8 @@ def __init__(self, alsru_cls):
         self.i_pc    = Signal(16)
         self.i_insn  = Signal(16, decoder=self._insn_decoder)
 
+        self.c_done  = Signal()
+
         self.o_pc_p1 = Signal(16)
         self.o_imm16 = Signal(16)
         self.o_rsd   = Signal(3)
@@ -152,6 +154,8 @@ def __init__(self, alsru_cls):
         self.o_ci    = self.CI.signal()
         self.o_si    = self.SI.signal()
 
+        self.r_exti  = Signal()
+
         self.m_imm   = ImmediateDecoder()
 
     def elaborate(self, platform):
@@ -461,6 +465,12 @@ def elaborate(self, platform):
                     self.o_skip.eq(1),
                 ]
 
+        with m.If(self.c_done):
+            m.d.sync += self.r_exti.eq(m_imm.c_exti)
+
+        with m.If(self.r_exti):
+            m.d.comb += m_imm.c_width.eq(m_imm.Width.IMM16)
+
         return m
 
 # -------------------------------------------------------------------------------------------------

diff --git a/boneless/test/test_instr_v3.py b/boneless/test/test_instr_v3.py
@@ -89,6 +89,16 @@ def test_negative_imm_lut(self):
         self.assertEqual(stream_1, stream_2)
         self.assertNotEqual(instr_1, instr_2)
 
+    def test_negative_imm_legal(self):
+        stream_1 = []
+        instr_1  = op.MOVI(op.R1, -10)
+        instr_1.encode(stream_1)
+        stream_2 = []
+        instr_2  = op.MOVI(op.R1, 65526)
+        instr_2.encode(stream_2)
+        self.assertEqual(stream_1, stream_2)
+        self.assertNotEqual(instr_1, instr_2)
+
     def test_roundtrip_negative_imm(self):
         instr = op.LD(op.R1, op.R0, -10)
         self.assertEqual(op.Instr.from_int(int(instr)), instr)