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base repository: whitequark/Boneless-CPU
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head repository: whitequark/Boneless-CPU
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compare: 83d7bad07b6b
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  • 4 commits
  • 3 files changed
  • 1 contributor

Commits on Jul 11, 2019

  1. gateware.decoder_v3: JR, JV and JT load Rsd to A, not Ra.

    @whitequark
    whitequark committed Jul 11, 2019
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    a28fe22 View commit details

  2. gateware.core_v3: alter PC in EXECUTE, not FETCH. 

    Change: -7 LUT.
    @whitequark
    whitequark committed Jul 11, 2019
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    bcd2f65 View commit details

  3. gateware.core_v3: wildcard match pointer loads. 

    Change: -6 LUT.
    @whitequark
    whitequark committed Jul 11, 2019
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    9b7f043 View commit details

  4. gateware.core_v3: deduplicate M adder. 

    Change: -16 LUT.
    @whitequark
    whitequark committed Jul 11, 2019
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    83d7bad View commit details
Showing with 25 additions and 19 deletions.
  1. +11 −6 boneless/gateware/core_v3.py
  2. +14 −13 boneless/gateware/decoder_v3.py
  3. BIN doc/design.ods
17 changes: 11 additions & 6 deletions boneless/gateware/core_v3.py
View file
Original file line number Diff line number Diff line change
@@ -148,6 +148,7 @@ def __init__(self, alsru_cls, reset_pc=0, reset_w=0xffff, memory=None):
self.r_f = Record([("z", 1), ("s", 1), ("c", 1), ("v", 1)])

self.r_insn = Signal(16)
self.s_base = Signal(16)
self.r_a = Signal(16)
self.s_b = Signal(16)
self.s_f = Record(self.r_f.layout)
@@ -206,6 +207,7 @@ def elaborate(self, platform):
m_arb.i_rsd.eq(m_dec.o_rsd),
m_arb.i_ra .eq(m_dec.o_ra),
m_arb.i_rb .eq(m_dec.o_rb),
m_arb.i_ptr.eq(self.s_base + m_dec.o_imm16)
]

m.submodules.alsru = m_alsru = self.m_alsru
@@ -238,9 +240,9 @@ def elaborate(self, platform):

with m.FSM():
m.d.comb += m_dec.i_insn.eq(self.r_insn)
m.d.comb += self.s_base.eq(self.r_a)

with m.State("FETCH"):
m.d.sync += self.r_pc.eq(m_dec.o_pc_p1)
m.d.comb += m_dec.c_done.eq(1)
m.d.comb += m_arb.c_op.eq(m_arb.Op.LD_PC)
m.next = "LOAD-A"
@@ -249,6 +251,8 @@ def elaborate(self, platform):
m.d.sync += self.r_insn.eq(m_arb.o_data)
m.d.comb += m_dec.i_insn.eq(m_arb.o_data)
with m.Switch(m_dec.o_ld_a):
with m.Case(m_dec.LdA.RSD):
m.d.comb += m_arb.c_op.eq(m_arb.Op.LD_RSD)
with m.Case(m_dec.LdA.RA):
m.d.comb += m_arb.c_op.eq(m_arb.Op.LD_RA)
m.next = "LOAD-B"
@@ -260,12 +264,12 @@ def elaborate(self, platform):
with m.Case(m_dec.LdA.W):
m.d.sync += self.r_a.eq(self.r_w << 3)
with m.Case(m_dec.LdA.PCp1):
m.d.sync += self.r_a.eq(self.r_pc)
with m.Case(m_dec.LdA.RA):
m.d.sync += self.r_a.eq(m_dec.o_pc_p1)
with m.Case(m_dec.LdX_PTR):
m.d.sync += self.r_a.eq(m_arb.o_data)
m.d.comb += self.s_base.eq(m_arb.o_data)
with m.Switch(m_dec.o_ld_b):
with m.Case(m_dec.LdB.ApI):
m.d.comb += m_arb.i_ptr.eq(self.m_arb.o_data + m_dec.o_imm16)
m.d.comb += m_arb.c_op.eq(
Mux(m_dec.o_xbus, m_arb.Op.LD_EXT, m_arb.Op.LD_MEM))
with m.Case(m_dec.LdB.RSD):
@@ -278,11 +282,10 @@ def elaborate(self, platform):
with m.Switch(m_dec.o_ld_b):
with m.Case(m_dec.LdB.IMM):
m.d.comb += self.s_b.eq(m_dec.o_imm16)
with m.Case(m_dec.LdB.ApI, m_dec.LdB.RSD, m_dec.LdB.RB):
with m.Case(m_dec.LdX_PTR):
m.d.comb += self.s_b.eq(m_arb.o_data)
with m.Switch(m_dec.o_st_r):
with m.Case(m_dec.StR.ApI):
m.d.comb += m_arb.i_ptr.eq(self.r_a + m_dec.o_imm16)
m.d.comb += m_arb.c_op.eq(
Mux(m_dec.o_xbus, m_arb.Op.ST_EXT, m_arb.Op.ST_MEM))
with m.Case(m_dec.StR.RSD):
@@ -296,6 +299,8 @@ def elaborate(self, platform):
m.d.sync += self.r_w .eq(m_alsru.o >> 3)
with m.If(m_dec.o_st_pc):
m.d.sync += self.r_pc.eq(m_alsru.o)
with m.Else():
m.d.sync += self.r_pc.eq(m_dec.o_pc_p1)
m.d.comb += self.o_done.eq(1)
m.next = "FETCH"

27 changes: 14 additions & 13 deletions boneless/gateware/decoder_v3.py
View file
Original file line number Diff line number Diff line change
@@ -29,7 +29,7 @@ def __init__(self):
self.c_exti = Signal()
self.c_table = self.Table.signal()
self.c_width = self.Width.signal()
self.c_addpc = Signal()
self.c_pcrel = Signal()

self.r_ext13 = Signal(13)

@@ -62,21 +62,22 @@ def elaborate(self, platform):
with m.Case(self.Width.IMM16):
m.d.comb += s_imm16.eq(Cat(d_imm3, self.r_ext13))

with m.If(self.c_addpc):
m.d.comb += self.o_imm16.eq(s_imm16 + self.i_pc)
with m.If(self.c_pcrel):
m.d.comb += self.o_imm16.eq(s_imm16 + self.i_pc + 1)
with m.Else():
m.d.comb += self.o_imm16.eq(s_imm16)

return m


class InstructionDecoder(Elaboratable):
CTRL_LD_PTR = 0b1_00
LdX_PTR = "1--"

class LdA(ControlEnum):
ZERO = 0b0_00
W = 0b0_01
PCp1 = 0b0_10
RSD = 0b1_01
RA = 0b1_10

class LdB(ControlEnum):
@@ -321,9 +322,9 @@ def elaborate(self, platform):
]
with m.Switch(self.i_insn):
with m.Case(opcode.M_ABS.coding):
m.d.comb += m_imm.c_addpc.eq(0)
m.d.comb += m_imm.c_pcrel.eq(0)
with m.Case(opcode.M_REL.coding):
m.d.comb += m_imm.c_addpc.eq(1)
m.d.comb += m_imm.c_pcrel.eq(1)
with m.Switch(self.i_insn):
with m.Case(opcode.C_LD.coding):
m.d.comb += [
@@ -367,9 +368,9 @@ def elaborate(self, platform):
with m.Case(opcode.C_MOVE.coding):
with m.Switch(self.i_insn):
with m.Case(opcode.M_ABS.coding):
m.d.comb += m_imm.c_addpc.eq(0)
m.d.comb += m_imm.c_pcrel.eq(0)
with m.Case(opcode.M_REL.coding):
m.d.comb += m_imm.c_addpc.eq(1)
m.d.comb += m_imm.c_pcrel.eq(1)
m.d.comb += [
m_imm.c_width.eq(m_imm.Width.IMM8),
self.o_ld_a.eq(self.LdA.ZERO),
@@ -414,23 +415,23 @@ def elaborate(self, platform):
# Jumps
with m.Case(opcode.T_JR.coding):
m.d.comb += [
self.o_ld_a.eq(self.LdA.RA),
self.o_ld_a.eq(self.LdA.RSD),
self.o_ld_b.eq(self.LdB.IMM),
self.o_op.eq(alsru_cls.Op.ApB),
self.o_st_pc.eq(1),
]
with m.Case(opcode.T_JV.coding):
m.d.comb += [
self.o_ld_a.eq(self.LdA.RA),
self.o_ld_a.eq(self.LdA.RSD),
self.o_ld_b.eq(self.LdB.ApI),
self.o_op.eq(alsru_cls.Op.ApB),
self.o_st_pc.eq(1),
]
with m.Case(opcode.T_JT.coding):
m.d.comb += [
m_imm.c_addpc.eq(1),
m_imm.c_pcrel.eq(1),
self.o_multi.eq(1),
self.o_ld_a.eq(self.LdA.RA),
self.o_ld_a.eq(self.LdA.RSD),
self.o_ld_b.eq(self.LdB.ApI),
self.o_op.eq(alsru_cls.Op.ApB),
self.o_st_pc.eq(1),
@@ -496,7 +497,7 @@ def elaborate(self, platform):
ports = (
dut.i_pc, dut.i_insn,
dut.o_imm16,
dut.c_exti, dut.c_table, dut.c_width, dut.c_addpc,
dut.c_exti, dut.c_table, dut.c_width, dut.c_pcrel,
)

if args.type == "instruction":
Binary file modified doc/design.ods
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