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base repository: m-labs/nmigen
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base: 2fa858b00342
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head repository: m-labs/nmigen
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compare: 278b624c66ad
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jul 10, 2019

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    278b624 View commit details
Showing with 2 additions and 2 deletions.
  1. +2 −2 nmigen/back/pysim.py
4 changes: 2 additions & 2 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -543,7 +543,7 @@ def add_domain_signal(signal, domain):
if signal.decoder:
var_type = "string"
var_size = 1
var_init = signal.decoder(signal.reset).replace(" ", "_")
var_init = signal.decoder(signal.reset).expandtabs().replace(" ", "_")
else:
var_type = "wire"
var_size = signal.nbits
@@ -649,7 +649,7 @@ def _commit_signal(self, signal_slot, domains):
for vcd_signal in self._vcd_signals[signal_slot]:
signal = self._slot_signals[signal_slot]
if signal.decoder:
var_value = signal.decoder(new).replace(" ", "_")
var_value = signal.decoder(new).expandtabs().replace(" ", "_")
else:
var_value = new
vcd_timestamp = (self._timestamp + self._delta) / self._epsilon