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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: f22106e5ef00
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Apr 20, 2019

  1. back.rtlil: allow record slices on LHS.

    whitequark committed Apr 20, 2019
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    f22106e View commit details
Showing with 2 additions and 2 deletions.
  1. +2 −2 nmigen/back/rtlil.py
4 changes: 2 additions & 2 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@
from contextlib import contextmanager

from ..tools import bits_for
from ..hdl import ast, ir, mem, xfrm
from ..hdl import ast, rec, ir, mem, xfrm


__all__ = ["convert"]
@@ -563,7 +563,7 @@ def on_Signal(self, value):
return wire_next

def _prepare_value_for_Slice(self, value):
assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat))
assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat, rec.Record))
return self(value)

def on_Part(self, value):