I would think that most SRAMs don't get reset on ASICs either, so that shouldn't interfere with BRAM inference.

I would think that most SRAMs don't get reset on ASICs either, so that shouldn't interfere with BRAM inference.

The problem isn't that the SRAM itself gets reset, but that you might want to fold address or data registers into an SRAM core. This is less of a problem in nMigen than in Verilog because some registers are implicit in the read port, but it's still a problem if a few of them are pipelined; e.g. Xilinx offers this as an option on BRAMs.

Of course if you're making an ASIC you can just make those registers with an asynchronous reset, so asynchronous reset isn't a problem there, but I didn't say it is.

Ah, missed that.