WIP merge CI+SI in ALSRU

whitequark · Aug 24, 2019 · 0253454 · 0253454
1 parent c6f00b2
commit 0253454
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Showing 3 changed files with 17 additions and 20 deletions.
diff --git a/boneless/gateware/alsru.py b/boneless/gateware/alsru.py
@@ -112,13 +112,14 @@ def elaborate(self, platform):
         op = self.Op.expand(m, self.op)
 
         s = Signal.like(self.o)
+        so = Signal()
         with m.Switch(op.s):
             with m.Case(self.MuxS.L):
-                m.d.comb += s.eq(Cat(self.si, self.r[:-1]))
-                m.d.comb += self.so.eq(self.r[-1])
+                m.d.comb += s.eq(Cat(self.ci, self.r[:-1]))
+                m.d.comb += so.eq(self.r[-1])
             with m.Case(self.MuxS.R):
-                m.d.comb += s.eq(Cat(self.r[ 1:], self.si))
-                m.d.comb += self.so.eq(self.r[ 0])
+                m.d.comb += s.eq(Cat(self.r[ 1:], self.ci))
+                m.d.comb += so.eq(self.r[ 0])
 
         x = Signal.like(self.o)
         with m.Switch(op.x):
@@ -143,13 +144,16 @@ def elaborate(self, platform):
                 m.d.comb += y.eq(~self.b)
 
         p = Signal.like(self.o)
-        m.d.comb += Cat(p, self.co).eq(x + y + self.ci)
+        co = Signal()
+        m.d.comb += Cat(p, co).eq(x + y + self.ci)
 
         with m.Switch(op.o):
             with m.Case(self.MuxO.XpY):
                 m.d.comb += self.o.eq(p)
+                m.d.comb += self.co.eq(co)
             with m.Case(self.MuxO.Y):
                 m.d.comb += self.o.eq(y)
+                m.d.comb += self.co.eq(so)
 
         # http://teaching.idallen.com/cst8214/08w/notes/overflow.txt
         with m.Switch(Cat(x[-1], y[-1], self.o[-1])):

diff --git a/boneless/gateware/core.py b/boneless/gateware/core.py
@@ -226,11 +226,8 @@ def elaborate(self, platform):
                 m.d.comb += m_alsru.ci.eq(1)
             with m.Case(m_dec.CI.FLAG):
                 m.d.comb += m_alsru.ci.eq(self.r_f.c)
-        with m.Switch(m_dec.o_si):
-            with m.Case(m_dec.SI.ZERO):
-                m.d.comb += m_alsru.si.eq(0)
-            with m.Case(m_dec.SI.MSB):
-                m.d.comb += m_alsru.si.eq(m_alsru.r[-1])
+            with m.Case(m_dec.CI.MSB):
+                m.d.comb += m_alsru.ci.eq(m_alsru.r[-1])
 
         m.submodules.shift = m_shift = self.m_shift
         m.d.comb += [

diff --git a/boneless/gateware/decoder.py b/boneless/gateware/decoder.py
@@ -114,10 +114,7 @@ class CI(ControlEnum):
         ZERO  = 0b00
         ONE   = 0b01
         FLAG  = 0b10
-
-    class SI(ControlEnum):
-        ZERO  = 0b0
-        MSB   = 0b1
+        MSB   = 0b11
 
     class Cond(ControlEnum):
         Z     = 0b000
@@ -169,7 +166,6 @@ def __init__(self, alsru_cls):
 
         self.o_op    = alsru_cls.Op.signal()
         self.o_ci    = self.CI.signal()
-        self.o_si    = self.SI.signal()
 
         self.r_exti  = Signal()
 
@@ -310,22 +306,22 @@ def elaborate(self, platform):
                 with m.Switch(self.i_insn):
                     with m.Case(opcode.T_SLL.coding):
                         m.d.comb += [
-                            self.o_si.eq(self.SI.ZERO),
+                            self.o_ci.eq(self.CI.ZERO),
                             self.o_op.eq(alsru_cls.Op.SL),
                         ]
                     with m.Case(opcode.T_ROT.coding):
                         m.d.comb += [
-                            self.o_si.eq(self.SI.MSB),
+                            self.o_ci.eq(self.CI.MSB),
                             self.o_op.eq(alsru_cls.Op.SL),
                         ]
                     with m.Case(opcode.T_SRL.coding):
                         m.d.comb += [
-                            self.o_si.eq(self.SI.ZERO),
+                            self.o_ci.eq(self.CI.ZERO),
                             self.o_op.eq(alsru_cls.Op.SR),
                         ]
                     with m.Case(opcode.T_SRA.coding):
                         m.d.comb += [
-                            self.o_si.eq(self.SI.MSB),
+                            self.o_ci.eq(self.CI.MSB),
                             self.o_op.eq(alsru_cls.Op.SR),
                         ]
                 with m.If(self.c_cycle == 0):
@@ -551,7 +547,7 @@ def elaborate(self, platform):
             dut.o_pc_p1, dut.o_imm16, dut.o_rsd, dut.o_ra, dut.o_rb, dut.o_cond, dut.o_flag,
             dut.o_shift, dut.o_multi, dut.o_xbus, dut.o_skip,
             dut.o_ld_a, dut.o_ld_b, dut.o_st_r, dut.o_st_w, dut.o_st_pc,
-            dut.o_op, dut.o_ci, dut.o_si,
+            dut.o_op, dut.o_ci,
         )
 
     cli.main_runner(parser, args, dut, ports=ports)