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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: 72cf4ca9914b
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Aug 23, 2019

  1. back.pysim: implement sim.add_clock(if_exists=True).

    whitequark committed Aug 23, 2019
    Copy the full SHA
    72cf4ca View commit details
Showing with 13 additions and 5 deletions.
  1. +6 −3 nmigen/back/pysim.py
  2. +7 −2 nmigen/test/test_sim.py
9 changes: 6 additions & 3 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -438,7 +438,7 @@ def sync_process():
sync_process = sync_process()
self.add_process(sync_process)

def add_clock(self, period, phase=None, domain="sync"):
def add_clock(self, period, *, phase=None, domain="sync", if_exists=False):
if self._fastest_clock == self._epsilon or period < self._fastest_clock:
self._fastest_clock = period
if domain in self._all_clocks:
@@ -453,8 +453,11 @@ def add_clock(self, period, phase=None, domain="sync"):
clk = domain_obj.clk
break
else:
raise ValueError("Domain '{}' is not present in simulation"
.format(domain))
if if_exists:
return
else:
raise ValueError("Domain '{}' is not present in simulation"
.format(domain))
def clk_process():
yield Passive()
yield Delay(phase)
9 changes: 7 additions & 2 deletions nmigen/test/test_sim.py
Original file line number Diff line number Diff line change
@@ -403,7 +403,7 @@ def test_add_process_wrong(self):
"a generator function"):
sim.add_process(1)

def test_add_clock_wrong(self):
def test_add_clock_wrong_twice(self):
m = Module()
s = Signal()
m.d.sync += s.eq(0)
@@ -413,13 +413,18 @@ def test_add_clock_wrong(self):
msg="Domain 'sync' already has a clock driving it"):
sim.add_clock(1)

def test_add_clock_wrong(self):
def test_add_clock_wrong_missing(self):
m = Module()
with self.assertSimulation(m) as sim:
with self.assertRaises(ValueError,
msg="Domain 'sync' is not present in simulation"):
sim.add_clock(1)

def test_add_clock_if_exists(self):
m = Module()
with self.assertSimulation(m) as sim:
sim.add_clock(1, if_exists=True)

def test_eq_signal_unused_wrong(self):
self.setUp_lhs_rhs()
self.s = Signal()