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base repository: m-labs/nmigen
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base: 9350620f89db
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head repository: m-labs/nmigen
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compare: 906385c7f8d6
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Aug 23, 2019

  1. Copy the full SHA
    906385c View commit details
Showing with 11 additions and 0 deletions.
  1. +4 −0 nmigen/back/pysim.py
  2. +7 −0 nmigen/test/test_sim.py
4 changes: 4 additions & 0 deletions nmigen/back/pysim.py
Original file line number Diff line number Diff line change
@@ -451,6 +451,10 @@ def add_clock(self, period, phase=None, domain="sync"):
for domain_obj in self._domains:
if not domain_obj.local and domain_obj.name == domain:
clk = domain_obj.clk
break
else:
raise ValueError("Domain '{}' is not present in simulation"
.format(domain))
def clk_process():
yield Passive()
yield Delay(phase)
7 changes: 7 additions & 0 deletions nmigen/test/test_sim.py
Original file line number Diff line number Diff line change
@@ -413,6 +413,13 @@ def test_add_clock_wrong(self):
msg="Domain 'sync' already has a clock driving it"):
sim.add_clock(1)

def test_add_clock_wrong(self):
m = Module()
with self.assertSimulation(m) as sim:
with self.assertRaises(ValueError,
msg="Domain 'sync' is not present in simulation"):
sim.add_clock(1)

def test_eq_signal_unused_wrong(self):
self.setUp_lhs_rhs()
self.s = Signal()