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I've been looking at implementing a JTAG TAP in nMigen, and according to IEEE 1149, a TAP is triggered by a clock negedge. Although one could add an inverter to the clock and hope it gets optimized out, native support for negedge triggered logic is easy to add, does not introduce any additional complexity in pysim, and would handle this nicely.
The text was updated successfully, but these errors were encountered:
I've been looking at implementing a JTAG TAP in nMigen, and according to IEEE 1149, a TAP is triggered by a clock negedge. Although one could add an inverter to the clock and hope it gets optimized out, native support for negedge triggered logic is easy to add, does not introduce any additional complexity in pysim, and would handle this nicely.
The text was updated successfully, but these errors were encountered: