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(nmigen) [verhaegs@localhost nmigen]$ ./atlys_bug.py
Traceback (most recent call last):
File "./atlys_bug.py", line 27, in <module>
products = p.build(test)
File "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/build/plat.py", line 47, in build
plan = self.prepare(fragment, name, **kwargs)
File "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/build/plat.py", line 73, in prepare
add_pin_fragment(pin, self.get_output(pin, port, attrs, invert))
File "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/vendor/xilinx_spartan_3_6.py", line 300, in get_output
o_O=port[bit]
File "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/dsl.py", line 88, in __setitem__
return self.__setattr__(name, value)
File "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/dsl.py", line 85, in __setattr__
self._builder._add_submodule(submodule, name)
File "/home/verhaegs/anaconda2/envs/nmigen/lib/python3.7/site-packages/nmigen/hdl/dsl.py", line 432, in _add_submodule
raise NameError("Submodule named '{}' already exists".format(name))
NameError: Submodule named 'ddr2_0__a' already exists
I tried to reproduce it with (sub)signals in other platform but did not succeed. Reverting 698b005 removes the problem.
The text was updated successfully, but these errors were encountered:
After yesterdays commit 698b005 I get following error when using ddr2.a from AtlysPlatform (pull-request m-labs/nmigen-boards#15).
Python code:
And this is the trace-back:
I tried to reproduce it with (sub)signals in other platform but did not succeed. Reverting 698b005 removes the problem.
The text was updated successfully, but these errors were encountered: