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base repository: m-labs/nmigen
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compare: 5fd8a796ae39
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  • 1 commit
  • 4 files changed
  • 1 contributor

Commits on Jul 21, 2019

  1. vendor: don't emit duplicate iobuf submodule names.

    These are no longer allowed after commit 698b005.
    nakengelhardt authored and whitequark committed Jul 21, 2019
    Copy the full SHA
    5fd8a79 View commit details
Showing with 26 additions and 26 deletions.
  1. +8 −8 nmigen/vendor/lattice_ecp5.py
  2. +2 −2 nmigen/vendor/lattice_ice40.py
  3. +8 −8 nmigen/vendor/xilinx_7series.py
  4. +8 −8 nmigen/vendor/xilinx_spartan_3_6.py
16 changes: 8 additions & 8 deletions nmigen/vendor/lattice_ecp5.py
Original file line number Diff line number Diff line change
@@ -272,7 +272,7 @@ def get_input(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("IB",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
i_I=port[bit],
o_O=i[bit]
)
@@ -284,7 +284,7 @@ def get_output(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("OB",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
i_I=o[bit],
o_O=port[bit]
)
@@ -296,7 +296,7 @@ def get_tristate(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("OBZ",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=port[bit]
@@ -310,7 +310,7 @@ def get_input_output(self, pin, port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("BB",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@@ -324,7 +324,7 @@ def get_diff_input(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("IB",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
i_I=p_port[bit],
o_O=i[bit]
)
@@ -336,7 +336,7 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("OB",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
i_I=o[bit],
o_O=p_port[bit],
)
@@ -348,7 +348,7 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("OBZ",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
i_T=t,
i_I=o[bit],
o_O=p_port[bit],
@@ -362,7 +362,7 @@ def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("BB",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
i_T=t,
i_I=o[bit],
o_O=i[bit],
4 changes: 2 additions & 2 deletions nmigen/vendor/lattice_ice40.py
Original file line number Diff line number Diff line change
@@ -253,9 +253,9 @@ def get_oxor(a, invert):
io_args.append(("i", "OUTPUT_ENABLE", pin.oe))

if is_global_input:
m.submodules[pin.name] = Instance("SB_GB_IO", *io_args)
m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_GB_IO", *io_args)
else:
m.submodules[pin.name] = Instance("SB_IO", *io_args)
m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_IO", *io_args)

def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs,
16 changes: 8 additions & 8 deletions nmigen/vendor/xilinx_7series.py
Original file line number Diff line number Diff line change
@@ -245,7 +245,7 @@ def get_input(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("IBUF",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
i_I=port[bit],
o_O=i[bit]
)
@@ -257,7 +257,7 @@ def get_output(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("OBUF",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
i_I=o[bit],
o_O=port[bit]
)
@@ -269,7 +269,7 @@ def get_tristate(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("OBUFT",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
i_T=t,
i_I=o[bit],
o_O=port[bit]
@@ -283,7 +283,7 @@ def get_input_output(self, pin, port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("IOBUF",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@@ -297,7 +297,7 @@ def get_diff_input(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("IBUFDS",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
i_I=p_port[bit], i_IB=n_port[bit],
o_O=i[bit]
)
@@ -309,7 +309,7 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("OBUFDS",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
)
@@ -321,7 +321,7 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("OBUFTDS",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
i_T=t,
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
@@ -335,7 +335,7 @@ def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("IOBUFDS",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
i_T=t,
i_I=o[bit],
o_O=i[bit],
16 changes: 8 additions & 8 deletions nmigen/vendor/xilinx_spartan_3_6.py
Original file line number Diff line number Diff line change
@@ -283,7 +283,7 @@ def get_input(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("IBUF",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
i_I=port[bit],
o_O=i[bit]
)
@@ -295,7 +295,7 @@ def get_output(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("OBUF",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
i_I=o[bit],
o_O=port[bit]
)
@@ -307,7 +307,7 @@ def get_tristate(self, pin, port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("OBUFT",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
i_T=t,
i_I=o[bit],
o_O=port[bit]
@@ -321,7 +321,7 @@ def get_input_output(self, pin, port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(port)):
m.submodules[pin.name] = Instance("IOBUF",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
i_T=t,
i_I=o[bit],
o_O=i[bit],
@@ -335,7 +335,7 @@ def get_diff_input(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("IBUFDS",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
i_I=p_port[bit], i_IB=n_port[bit],
o_O=i[bit]
)
@@ -347,7 +347,7 @@ def get_diff_output(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("OBUFDS",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
)
@@ -359,7 +359,7 @@ def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
m = Module()
i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("OBUFTDS",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
i_T=t,
i_I=o[bit],
o_O=p_port[bit], o_OB=n_port[bit]
@@ -373,7 +373,7 @@ def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
o_invert=True if invert else None)
for bit in range(len(p_port)):
m.submodules[pin.name] = Instance("IOBUFDS",
m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
i_T=t,
i_I=o[bit],
o_O=i[bit],